Nonvolatile semiconductor memory device capable of uniformly inputting/outputting data

Abstract

At the time of an operation of writing data to a specific memory cell in a memory block, a semiconductor memory device applies a write voltage for a predetermined period and, after that, performs a verifying operation by using a sense amplifier circuit and a comparator. When it is found as a result of the verifying operation that writing to the memory cell is insufficient, the writing operation is performed again by an instruction of a memory control circuit. At this time, the memory control circuit adjusts a write voltage.

Claims

1 - 10 . (canceled) 11 . A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a plurality of memory blocks including a plurality of nonvolatile memory cells arranged in a matrix; a plurality of word lines arranged in correspondence with a row direction of said plurality of memory cells; a plurality of bit lines arranged in correspondence with a column direction of said plurality of memory cells; and a control circuit for performing an erasing operation on said plurality of memory cells at the time of an erasing operation, wherein each of said plurality of memory cells includes: first and second conductive regions formed in a main surface of said semiconductor substrate and connected to corresponding bit lines in said plurality of bit lines; and an insulating film formed on said semiconductor substrate between said first and second conductive regions, having a first storing region in the vicinity of said first conductive region and a second storing region in the vicinity of said second conductive region, and said control circuit applies at least one pulse voltages to a selected memory cell in said plurality of memory cells. 12 . The nonvolatile semiconductor memory device according to claim 11 , further comprising a verifying circuit for performing a verifying operation on said selected memory cell each time said control circuit applies said pulse voltage. 13 . The nonvolatile semiconductor memory device according to claim 12 , wherein a voltage applied to said first conductive region at the time of the writing operation is higher than a voltage applied to said second conductive region, and a voltage applied to said first conductive region at the time of a reading operation is lower than a voltage applied to said second conductive region. 14 . The nonvolatile semiconductor memory device according to claim 11 , further comprising a sense amplifier circuit for reading data stored in each of the plurality of memory cells. 15 . The nonvolatile semiconductor memory device according to claim 14 , wherein said sense amplifier circuit is a single end type sense amplifier circuit. 16 . The nonvolatile semiconductor memory device according to claim 14 , wherein said sense amplifier circuit includes a differential amplifier circuit which receives data of each of said plurality of memory cells and a reference potential. 17 . The nonvolatile semiconductor memory device according to claim 16 , wherein said sense amplifier circuit further includes a reference potential generating circuit for generating said reference potential, and said reference potential generating circuit includes a plurality of reference cells operating at the time of a reading or erasing operation. 18 . The nonvolatile semiconductor memory device according to claim 17 , wherein said plurality of reference cells include: a read reference cell operating in a reading operation; and an erase reference cell operating in an erasing operation and having a threshold value different from that of said read reference cell. 19 . The nonvolatile semiconductor memory device according to claim 18 , wherein the threshold value of said erase reference cell is lower than the threshold value of said read reference cell.
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device capable of storing multi values. [0003] 2. Description of the Background Art [0004] Among nonvolatile semiconductor memory devices, attention is being paid to an NROM (Nitride Read Only Memory) type flash EEPROM (hereinafter, referred to as NROM) as a kind of a flash EEPROM. An NROM is disclosed in U.S. Pat. Nos. 6,011,725 and 5,768,192. [0005] FIG. 29 is a cross sectional view of a conventional flash EEPROM. [0006] Referring to FIG. 29 , a flash EEPROM includes a semiconductor substrate 1 , a drain region 2 , a source region 3 , a floating gate 4 , an insulating film 5 , and a control gate 6 . [0007] Drain region 2 and source region 3 are formed with a predetermined interval in the main surface of semiconductor substrate 1 . Floating gate 4 is formed on semiconductor substrate 1 between drain region 2 and source region 3 . Control gate 6 is formed on floating gate 4 . The surfaces of floating gate 4 and control gate 6 are covered with insulating film 5 . [0008] In the flash EEPROM, electrons are accumulated in floating gate 4 . Therefore, floating gate 4 is covered with insulating film 5 . Insulating film 5 prevents leakage of electrons from floating gate 4 . [0009] In the conventional flash EEPROM, it is difficult to thin insulating film 5 . If insulating film 5 is thin, electrons are leaked from floating gate 4 and, as a result, data written in the flash EEPROM is easily dissipated. Therefore, it is limited to make the flash EEPROM finer. [0010] FIG. 30 is a cross sectional view of a memory cell used for an NROM. [0011] Referring to FIG. 30 , the NROM includes semiconductor substrate 1 , two diffusion bit lines 7 A and 7 B, oxide films 8 and 10 , a nitride film 9 , and a control gate 11 . [0012] Two diffusion bit lines 7 A and 7 B are formed with a predetermined interval in the main surface of semiconductor substrate 1 . Oxide film 8 is formed on semiconductor substrate 1 between two diffusion bit lines. Nitride film 9 is formed on oxide film 8 . Oxide film 10 is formed on nitride fi 9 . Control gate 11 is formed on oxide film 10 . [0013] In the NROM, electrons can be accumulated in each of storing regions 9 L and 9 R in nitride film 9 . That is, by accumulating electrons in physically different two positions in one cell, the NROM can store data of two bits per cell. [0014] The electrons accumulated in storing regions 9 L and 9 R in nitride film 9 cannot freely move in nitride film 9 and remain in storing regions 9 L and 9 R for the reason that nitride film 9 is an insulating film. [0015] The NROM is easily manufactured and the price is low. A memory cell array to which the NROM is applied has a configuration that diffusion bit lines and word lines cross perpendicular to each other. A diffusion bit line is shared by adjoining memory cells. Consequently, the area of the memory cell array can be reduced as compared with the conventional flash EEPROM., [0016] An operation of writing data to the NROM is performed by injecting hot electrons to a channel. An operation of erasing data in the NROM is performed by injecting hot holes generated by tunneling between bands. In a reading mode, a current is passed in the direction opposite to that in a writing mode. The moving direction of electrons in the reading mode from storing region 9 L is therefore the same as that in the writing mode to storing region 9 R. [0017] FIGS. 31A to 31 D are diagrams showing the operations of writing/reading data to/from two storing regions 9 L and 9 R in an NROM type memory cell. [0018] Referring to FIG. 3 1 A, a memory cell MC is a memory cell of the NROM type. The gate of memory cell MC is connected to a word line WL. It is assumed that memory cell MC is connected to bit lines BL 0 and BL 1 . Memory cell MC has storing region 9 L on a bit line BL 0 side and has, as shown in FIG. 31C , storing region 9 R on bit line BL 1 side. [0019] First, the writing operation to storing region 9 L will be described. Referring to FIG. 31A , in the case of writing data to storing region 9 L, word line WL is activated. The potential of bit line BL 0 is maintained at a write potential VCCW, and the potential of bit line BL 1 is maintained at a ground potential GND. As a result, a write current Ifw flows from bit line BL 0 to bit line BL 1 via nonvolatile memory cell MC. At this time, data is written in storing region 9 L. [0020] Next, the operation of reading data from storing region 9 L will be described. Referring to FIG. 31B , in the case of reading data of storing region 9 L, word line WL is activated. The potential of bit line BL 0 is maintained at ground potential GND, and the potential of bit line BL 1 is maintained at a read potential VCCR. By detecting whether a read current Ifr flows from bit line BL 1 to bit line BL 0 , data is read. [0021] As described above, in storing region 9 L, the current direction in the writing operation and that in the reading operation are opposite to each other. [0022] The writing operation to storing region 9 R will now be described. Referring to FIG. 31C , in the case of writing data to storing region 9 R, word line WL is activated. The potential of bit line BL 0 is maintained at ground potential GND, and the potential of bit line BL 1 is maintained at write potential VCCW. As a result, write current Irw flows from bit line BL 1 to bit line BL 0 . At this time, data is written in storing region 9 R. [0023] Next, the operation of reading data from storing region 9 R will be described. Referring to FIG. 31D , in the case of reading data of storing region 9 R, word line WL is activated. The potential of bit line BL 0 is maintained at read potential VCCR and the potential of bit line BL 1 is maintained at ground potential GND. By detecting whether a read current Irr flows from bit line BL 0 to bit line BL 1 , data is read. [0024] As described above, in the writing operation of the NROM, if a predetermined potential is applied to each of diffusion bit line and control gate, electrons can be accumulated in storing region 9 L or 9 R. However, if a potential is excessively applied in the writing operation, the following problems occur. [0025] (1) There is the possibility that a threshold value of a memory cell becomes too high and data cannot be erased in a designated period in an erasing operation for the reason that if a potential is excessively applied at the time of a writing, excessive electrons are accumulated in nitride film 9 . This problem can happen also in a conventional flash EEPROM. [0026] (2) There is the possibility that data of two bits cannot be stored in each cell (hereinafter, referred to as two bits/cell). Specifically, in the NROM, it is necessary to accurately read storing region 9 R irrespective of the state of storing region 9 L and accurately read storing region 9 L irrespective of the state of storing region 9 R. [0027] FIGS. 32A and 32B are diagrams for describing the reading operation of the NROM. FIGS. 32A and 32B show the case where electrons are accumulated in storing region 9 L and electrons are not accumulated in storing region 9 R. [0028] FIG. 32A shows an NROM on which the writing operation is accurately performed, and FIG. 32B shows an NROM in which electrons are excessively accumulated in the writing operation. [0029] Referring to FIG. 32A , in the case of reading data from storing region 9 R, a predetermined potential is applied to diffusion bit line 7 and control gate 11 . At this time, a depletion layer is expanded to a range V in semiconductor substrate 1 . If the operation of writing data to storing region 9 L is performed normally, the distribution of electrons stored-in storing region 9 L lies within the range V. In this case, therefore, data of storing region 9 R is read normally. [0030] On the other hand, in the case of FIG. 32B , in the operation of reading data from storing region 9 R, the depletion layer is expanded to the range V. However, a potential is excessively applied at the time of writing data to storing region 9 L, the electron distribution expands to a range E. In the case of reading data from storing region 9 R, due to the electron distribution exceeding the range V of the depletion layer, the threshold value increases. As a result, it may be erroneously recognized that storing region 9 R is in a programmed state. This problem does not occur in a conventional flash EEPROM using the floating gate. [0031] (3) There is the possibility that, in the writing operation, a part of electrons to be accumulated in storing regions 9 L and 9 R is accumulated in a position apart from each diffusion bit line. [0032] FIG. 33 is a schematic diagram showing a state where a part of electrons is accumulated in a position apart from each diffusion bit line in the writing operation. [0033] In FIG. 33 , a part of electrons is stored in regions 12 and 13 apart from diffusion bit lines 7 A and 7 B, respectively. [0034] In the case where electrons are stored in positions as shown in FIG. 33 , even if a specific erase voltage is applied, all of the accumulated electrons cannot be erased. A region in which a strong electric field is generated when the erase voltage is applied is a portion in which the control gate and each diffusion bit line are adjacent to each other. The electrons accumulated in the adjacent portion are neutralized with holes injected at the time of erasing in the whole regions 9 L and 9 R. However, in the case where electrons are accumulated in positions such as regions 12 and 13 as shown in FIG. 33 , a sufficient electric field is not applied to the regions in which a part of electrons are accumulated, so that holes for neutralizing electrons stored in the region are not sufficiently injected. As a result, the electrons in regions 12 and 13 are not neutralized as a whole. Therefore, the threshold value does not decrease after the erasing operation, so that resistance characteristic of the NROM deteriorates. This problem occurs due to a property peculiar to the NROM such that electrons cannot move in the electron accumulating layer at the time of programming. In a conventional flash EEPROM, as electrons and holes can freely move in the floating gate, such a problem cannot occur. [0035] In order to solve the problems, it is necessary to suppress variations in the threshold value of a memory cell in the writing and erasing operations. That is, it is necessary to prevent application of an excessive write voltage at the time of a writing operation. SUMMARY OF THE INVENTION [0036] Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory device capable of suppressing variations in a threshold value of a memory cell. [0037] A nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate, a plurality of memory blocks, a plurality of word lines, a plurality of bit lines, and a control circuit. The plurality of memory blocks includes a plurality of nonvolatile memory cells arranged in a matrix. The plurality of word lines are arranged in correspondence with a row direction of the plurality of memory cells. The plurality of bit lines are arranged in correspondence with a column direction of the plurality of memory cells. The control circuit performs a writing operation on the plurality of memory cells at the time of a writing operation. Each of the plurality of memory cells includes first and second conductive regions and an insulating film. The first and second conductive regions are formed in a main surface of the semiconductor substrate and connected to corresponding bit lines in the plurality of bit lines. The insulating film is formed on the semiconductor substrate between the first and second conductive regions, and has a first storing region in the vicinity of the first conductive region and a second storing region in the vicinity of the second conductive region. The control circuit applies at least one pulse voltages to a selected memory cell in the plurality of memory cells. [0038] With the configuration, the nonvolatile semiconductor memory device according to the present invention can perform the writing operation on a memory cell step by step. Thus, supply of excessive charges to a memory cell by performing the writing operation at a time can be prevented. [0039] A nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate, a plurality of memory blocks, a plurality of word lines, a plurality of bit lines, and a control circuit. The plurality of memory blocks include a plurality of nonvolatile memory cells arranged in a matrix. The plurality of word lines are arranged in correspondence with a row direction of the plurality of memory cells. The plurality of bit lines are arranged in correspondence with a column direction of the plurality of memory cells. The control circuit performs an erasing operation on the plurality of memory cells at the time of an erasing operation. Each of the plurality of memory cells includes first and second conductive regions and an insulating film. The first and second conductive regions are formed in a main surface of the semiconductor substrate and connected to corresponding bit lines in the-plurality of bit lines. The insulating film is formed on the semiconductor substrate between the first and second conductive regions, and has a first storing region in the vicinity of the first conductive region and a second storing region in the vicinity of the second conductive region. The control circuit applies at least one pulse voltages to a selected memory cell in the plurality of memory cells. [0040] With the configuration, the nonvolatile semiconductor memory device according to the present invention can perform the erasing operation on a memory cell step by step. [0041] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0042] FIG. 1 is a circuit block diagram showing the configuration of a nonvolatile semiconductor memory device in a first embodiment of the present invention; [0043] FIG. 2 is a circuit diagram showing the configuration of a memory block in FIG. 1 ; [0044] FIG. 3 is a block diagram showing the configuration of a bit line control circuit in FIG. 1 ; [0045] FIG. 4 is a block diagram showing the configuration of a core circuit in FIG. 3 ; [0046] FIG. 5 is a circuit diagram showing the configuration of a first column selector in FIG. 4 ; [0047] FIG. 6 is a circuit diagram showing the configuration of a second column selector in FIG. 4 ; [0048] FIG. 7 is a circuit diagram showing the configuration of a potential control circuit in FIG. 4 ; [0049] FIG. 8 is a block diagram showing the configuration of a sense amplifier circuit in FIG. 1 ; [0050] FIG. 9 is a circuit diagram showing the configuration of a sense amplifier in FIG. 8 ; [0051] FIG. 10 is a circuit diagram showing another configuration of the sense amplifier in FIG. 8 ; [0052] FIG. 11 is a block diagram showing the configuration of a row decoder in FIG. 1 ; [0053] FIG. 12 is a circuit diagram showing the configuration of a word driver in FIG. 11 ; [0054] FIG. 13 is a block diagram showing the configuration of a memory control circuit in FIG. 1 ; [0055] FIG. 14 is a circuit diagram showing the configuration of an SHV detecting circuit in FIG. 13 ; [0056] FIG. 15 is a flowchart showing a writing operation of the semiconductor memory device in the first embodiment of the present invention; [0057] FIG. 16 is a timing chart at the time of the writing operation of the semiconductor memory device in the first embodiment of the present invention; [0058] FIG. 17 is a timing chart showing the operation of each of circuits in the semiconductor memory device at the time of the writing operation; [0059] FIG. 18 is a timing chart showing the operation of each of circuits in the semiconductor memory device at the time of an erasing operation; [0060] FIG. 19 is a flowchart showing the writing operation of a semiconductor memory device in a second embodiment of the present invention; [0061] FIG. 20 is a timing chart at the time of a writing operation of the semiconductor memory device in the second embodiment of the present invention; [0062] FIG. 21 is a timing chart showing operations of circuits in the semiconductor memory device in the writing operation; [0063] FIG. 22 is a circuit diagram showing the configuration of an HV detecting circuit of a semiconductor memory device in the third embodiment of the present invention; [0064] FIG. 23 is a timing chart at the time of the writing operation of the semiconductor memory device in the third embodiment of the present invention; [0065] FIG. 24 is a block diagram showing a memory control circuit of a semiconductor memory device in a fourth embodiment of the present invention; [0066] FIG. 25 is a flowchart showing the writing operation of the semiconductor memory device in the fourth embodiment; [0067] FIGS. 26A and 26B are graphs showing resistance to the total number of writing operations in a flash EEPROM and that in an NROM; [0068] FIG. 27 is a block diagram showing the configuration of a memory control circuit of a semiconductor memory device in a fifth embodiment of the present invention; [0069] FIG. 28 is a cross sectional view of an NROM using a polysilicon film as a charge accumulating layer; [0070] FIG. 29 is a cross sectional view of a conventional flash EEPROM; [0071] FIG. 30 is a cross sectional view of an NROM; [0072] FIGS. 31A to 31 D are diagrams showing operations of writing/reading data to/from two storing regions 9 L and 9 R in an NROM type memory cell; [0073] FIGS. 32A and 32B are diagrams for describing a reading operation of an NROM; and [0074] FIG. 33 is a schematic diagram showing a state where electrons are stored in a position apart from each diffusion bit line at the time of a writing operation. DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment [0075] Embodiments of the present invention will be described in detail hereinafter. The same reference numerals are designated to the same or corresponding parts and the description will not be repeated. [0076] FIG. 1 is a circuit block diagram showing the configuration of a nonvolatile semiconductor memory device in a first embodiment of the present invention. [0077] Referring to FIG. 1 , a nonvolatile semiconductor memory device 100 includes a memory cell array 20 , a bit line control circuit 21 , a sense amplifier circuit 22 , a first multiplexer 23 , an output buffer 24 , a comparator 25 , a second multiplexer 26 , an input buffer 27 , a memory control circuit 28 , and a row decoder 29 . [0078] Memory cell array 20 includes a plurality of memory blocks MB [m, n]. “m” is a natural number and indicates the row number of a memory block. “n” is a natural number and indicates the column number of a memory block. For example, a memory block MB [ 8 , 64 ] denotes the memory block positioned in the eighth row and 64th column. [0079] For memory blocks MB [m, n] in the same column, main bit lines MBL ( 4 n - 3 ) to MBL ( 4 n ) are disposed. For example, for a plurality of memory blocks MB [m, 1 ] positioned in the first column, main bit lines MBL 1 to MBL 4 are disposed. [0080] FIG. 2 is a circuit diagram showing the configuration of a memory block in FIG. 1 . [0081] Memory block MB [m, n] includes a plurality of memory cells MC, a plurality of word lines WLk (k denotes an integer including 0), N-channel MOS transistors QN 1 to QN 8 , signal lines S 1 to S 4 , and diffusion bit lines BL 0 to BL 7 . [0082] Plurality of word lines WLk are arranged in the row direction and diffusion bit lines BL 0 to BL 7 are arranged in the column direction. [0083] Each of the plurality of memory cells is a nonvolatile memory cell capable of storing binary data which is, for example, an MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type memory cell. The sectional structure of the MONOS type memory cell is as shown in FIG. 30 . The plurality of memory cells MC are arranged at intersections of word lines WLk and diffusion bit lines BL 0 to BL 7 . The plurality of memory cells MC disposed in the same row are connected in series, and their gates are connected to the same word line WLk. Each of diffusion bit lines BL 0 to BL 7 is disposed so as to pass the connection point of adjoining two nonvolatile memory cells MC. [0084] Transistor QN 1 is connected between diffusion bit line BL 0 and main bit line MBL ( 4 n - 3 ), and its gate is connected to signal line S 1 . Transistor QN 2 is connected between main bit line MBL ( 4 n - 3 ) and diffusion bit-line BL 2 , and its gate is connected to signal line S 2 . Transistor QN 5 is connected between diffusion bit line BL 1 and main bit line MBL ( 4 n - 2 ), and its gate is connected to signal line S 3 . Transistor QN 6 is connected between main bit line MBL ( 4 n - 2 ) and diffusion bit line BL 3 , and its gate is connected to signal line S 4 . Transistor QN 3 is connected between diffusion bit line BL 4 and main bit line MBL ( 4 n - 1 ), and its-gate is connected to signal line S 1 . Transistor QN 4 is connected between main bit line MBL ( 4 n - 1 ) and diffusion bit line BL 6 , and its gate is connected to signal line S 2 . Transistor QN 7 is connected between diffusion bit line BL 5 and main bit line MBL ( 4 n ), and its gate is connected to signal line S 3 . Transistor QN 8 is connected between main bit line MBL ( 4 n ) and diffusion bit line BL 7 , and its gate is connected to signal line S 4 . [0085] Signal lines S 1 to S 4 are connected to memory control circuit 28 and transfer signals S 1 to S 4 , respectively. [0086] Referring again to FIG. 1 , bit line control circuit 21 is a circuit used for controlling the plurality of main bit lines MBL at the time of outputting/inputting data from/to memory cell array 20 . [0087] FIG. 3 is a block diagram showing the configuration of bit line control circuit 21 in FIG. 1 . Signals CS 0 to CS 7 , signals BS 0 to BS 15 , and control signals RE, PV, PG, EV, and ER are outputted from memory control circuit 28 . [0088] Referring to FIG. 3 , bit line control circuit 21 includes eight core circuits 211 to 218 . Al of core circuits 211 to 218 are connected to signal lines φA 1 to φA 4 . Signal line Al transfers signals CS 0 to CS 7 . Signal line φA 2 transfers signals BS 0 to BS 15 . Signal line φA 3 transfers internal data signals DIN 0 to DIN 7 . Signal line φA 4 transfers control signals RE, PV, PG, EV, and ER outputted from memory control circuit 28 . Signal PG is a signal which is activated when a write voltage is applied to a memory cell in the writing operation. Signal PV is a signal which is activated when a verifying operation is performed in the writing operation. Signal ER is a signal which is activated in an erasing operation. Signal EV is a signal which is activated at the time of performing the verifying operation in the erasing operation. Control signals PG and PV are outputted from memory control circuit 28 in the writing operation and control signals EV and ER are outputted from memory control circuit 28 in the erasing operation. Control signal RE is a signal which is activated in a reading operation and is outputted from memory control circuit 28 . [0089] Each of core circuits 211 to 218 is connected to 32 main bit lines MBL and outputs a signal OUT 1 to sense amplifier circuit 22 . Signal OUT 1 includes signals OUT 10 to OUT 17 . Core circuit 211 is connected to main bit lines MBL 1 to MBL 32 and outputs signal OUT 10 to sense amplifier circuit 22 in response to a signal outputted from memory control circuit 28 . Core circuit 212 is connected to main bit lines MBL 33 to MBL 64 and outputs signal OUT 11 to sense amplifier circuit 22 . Core circuit 213 is connected to main bit lines MBL 65 to MBL 96 and outputs signal OUT 12 to sense amplifier circuit 22 . Core circuit 214 is connected to main bit lines MBL 97 to MBL 128 and outputs signal OUT 13 to sense amplifier circuit 22 . Core circuit 215 is connected to main bit lines MBL 129 to MBL 160 and outputs signal OUT 14 to sense amplifier circuit 22 . Core circuit 216 is connected to main bit lines MBL 161 to MBL 192 and outputs signal OUT 15 to sense amplifier circuit 22 . Core circuit 217 is connected to main bit lines MBL 193 to MBL 224 and outputs signal OUT 16 to sense amplifier circuit 22 . Core circuit 218 is connected to main bit lines MBL 225 to MBL 256 and outputs signal OUT 17 to sense amplifier circuit 22 . [0090] FIG. 4 is a block diagram showing the configuration of a core circuit in FIG. 3 . Although core circuit 211 will be described by referring to FIG. 4 , the configuration of the other core circuits 212 to 218 is similar to that of core circuit 211 . [0091] Referring to FIG. 4 , core circuit 211 includes four first column selectors 31 to 34 , a second column selector 35 , and a potential control circuit 36 . [0092] First column selector 31 is connected to eight main bit lines MBL 1 to MBL 8 , receives signals CS 0 to CS 7 , and outputs signals EBL 0 and OBL 0 . First column selector 32 is connected to eight main bit lines MBL 9 to MBL 16 , receives signals CS 0 to CS 7 , and outputs signals EBL 1 and OBL 1 . First column selector 33 is connected to eight main bit lines MBL 17 to MBL 24 , receives signals CS 0 to CS 7 , and outputs signals EBL 2 and OBL 2 . First column selector 34 is connected to eight main bit lines MBL 25 to MBL 32 , receives signals CS 0 to CS 7 , and outputs signals EBL 3 and OBL 3 . [0093] Second column selector 35 receives signals EBL 0 to EBL 3 and OBL 0 to OBL 3 outputted from first column selectors 31 to 34 , and outputs signals B 1 and B 2 in response to signals BS 0 to BS 15 . [0094] Potential control circuit 36 receives signals B 1 and B 2 outputted from second column selector 35 and outputs signal OUT 10 to sense amplifier circuit 22 in response to an instruction of memory control circuit 28 . [0095] Since the configuration of each of the other core circuits 212 to 218 is the same as that of core circuit 211 , its description will not be repeated. [0096] FIG. 5 is a circuit diagram showing the configuration of a first column selector in FIG. 4 . [0097] Referring to FIG. 5 , first column selector 31 includes a plurality of N-channel MOS transistors QN 30 to QN 37 . [0098] Signal CS 0 is inputted to the gate of transistor QN 30 . Transistor QN 30 is connected between main bit line MBL 1 and a node N 31 . Transistor QN 31 is connected between main bit line MBL 2 and a node N 30 and receives signal CS 1 by its gate. Transistor QN 32 is connected between main bit line MBL 3 and node N 31 and receives signal CS 2 by its gate. Transistor QN 33 is connected between main bit line MBL 4 and node N 30 and receives signal CS 3 by its gate. Transistor QN 34 is connected between main bit line MBL 5 and node N 31 , and receives signal CS 4 by its gate. Transistor QN 35 is connected between main bit line MBL 6 and node N 30 and receives signal CS 5 by its gate. Transistor QN 36 is connected between main bit line MBL 7 and node N 31 and receives signal CS 6 by its gate. Transistor QN 37 is connected between main bit line MBL 8 and node N 30 and receives signal CS 7 by its gate. [0099] In response to signals CS 0 to CS 7 outputted from memory control circuit 28 , first column selector 31 outputs signal EBL 0 from node N 30 and outputs signal OBL 0 from node N 31 . [0100] Since the configuration of each of the other first column selectors 32 to 34 is the same as that of first column selector 31 , its description will not be repeated. [0101] FIG. 6 is a circuit diagram showing the configuration of a second column selector in FIG. 4 . [0102] Referring to FIG. 6 , second column selector 35 includes a plurality of N-channel MOS transistors QN 40 to QN 47 and P-channel MOS transistors QP 40 to QP 47 . Transistor QN 40 is connected between nodes N 42 and N 40 and receives signal BS 0 by its gate. Transistor QP 40 is connected between nodes N 42 and N 41 and receives signal BS 1 by its gate. Node N 42 receives signal OBL 0 outputted from first column selector 31 . Transistor QN 41 is connected between nodes N 43 and N 40 , and receives signal BS 2 by its gate. Transistor QP 41 is connected between nodes N 43 and N 41 and receives signal BS 3 by its gate. Node N 43 receives signal EBL 0 outputted from first column selector 31 . Tansistor QN 42 is connected between nodes N 44 and N 40 and receives signal BS 4 by its gate. Tansistor QP 42 is connected between nodes N 44 and N 41 , and receives signal BS 5 by its gate. Node N 44 receives signal OBL 1 outputted from first column selector 32 . Transistor QN 43 is connected between nodes N 45 and N 40 , and receives signal BS 6 by its gate. Transistor QP 43 is connected between nodes N 45 and N 41 , and receives signal BS 7 by its gate. Node N 45 receives signal EBL 1 outputted from first column selector 32 . Transistor QN 44 is connected between nodes N 46 and N 40 , and receives signal BS 8 by its gate. Transistor QP 44 is connected between nodes N 46 and N 41 and receives signal BS 9 by its gate. Node N 46 receives signal OBL 2 outputted from first column selector 33 . Tansistor QN 45 is connected between nodes N 47 and N 40 , and receives signal BS 10 by its gate. Transistor QP 45 is connected between nodes N 47 and N 41 and receives signal BS 11 by its gate. Node N 47 receives signal EBL 2 outputted from first column selector 33 . Transistor QN 46 is connected between nodes N 48 and N 40 , and receives signal BS 12 by its gate. Transistor QP 46 is connected between nodes N 48 and N 41 , and receives signal BS 13 by its gate. Node N 48 receives signal OBL 3 outputted from first column selector 34 . Transistor QN 47 is connected between nodes N 49 and N 40 and receives signal BS 14 by its gate. Transistor QP 47 is connected between nodes N 49 and N 41 and receives signal BS 15 by its gate. Node N 49 receives signal EBL 3 outputted from first column selector 34 . [0103] In response to signals BS 0 to. BS 15 outputted from memory control circuit 28 , second column selector 35 outputs signal B 1 from node N 40 and outputs signal B 2 from node N 41 . [0104] FIG. 7 is a circuit diagram showing the configuration of potential control circuit 36 in FIG. 4 . [0105] Referring to FIG. 7 , potential control circuit 36 includes switch circuits SW 1 to SW 3 , an inverter IV 1 , logic gates L 1 to L 3 , and an N-channel MOS transistor QN 51 . [0106] A signal line BO is connected to a potential SHV node 42 via switch circuit SW 1 , connected to a potential IV node 43 via switch circuit SW 2 , and connected to a power supply potential node 40 for outputting a potential of about 2V via switch circuit SW 3 . Signal line BO receives signal B 2 outputted from second column selector 35 and outputs it as signal OUT 1 . [0107] Inverter IV 1 receives signal ER outputted from memory control circuit 28 , inverts signal ER, and outputs the result as a signal E 8 . Logic gate L 2 receives signal PG outputted from memory control circuit 28 and internal data signal DIN 0 , and outputs a result of NOR operation as a signal E 5 . [0108] Logic gate L 3 receives signals RE, PV, and EV outputted from memory control circuit. 28 . When all of input signals RE, PV, and EV are at the H level, logic gate L 3 outputs-a signal E 2 of the L level. In-the other cases, logic gate L 3 outputs signal E 2 of the H level. [0109] Transistor QN 51 is connected between signal line BO and ground potential node 41 , and receives an output signal from logic gate L 1 by its gate. Logic gate L 1 receives signals E 8 , E 5 , and E 2 and, when all of signals E 8 , E 5 , and E 2 are at the L level, outputs the H-level signal. When the signal outputted from logic gate L 1 is at the H level, transistor QN 51 is turned on and the potential on signal line BO is maintained at the ground potential. [0110] Switch circuit SW 1 includes a plurality of N-channel MOS transistors QN 52 to QN 54 , QN 56 , and QN 57 , P-channel MOS transistors QP 52 to QP 57 , and an inverter IV 2 . Inverter IV 2 receives signal E 8 , inverts it, and outputs the resultant signal. [0111] Transistors QP 52 and QN 52 are connected in series between potential SHV node 42 and ground potential node 41 . Transistors QP 53 and QN 53 are connected in series between potential SHV node 42 and ground potential node 41 . The gate of transistor QP 52 is connected to the drain of transistor QN 53 . The gate of transistor QP 53 is connected to the drain of transistor QN 52 . The gate of transistor QN 52 receives an output signal of inverter IV 2 , and the gate of transistor QN 53 receives signal E 8 . Transistors QP 54 and QN 54 are connected in series between potential SHV node 42 and ground potential node 41 . The gate of transistor QP 54 is connected to the drain of transistor QN 53 . The gate of transistor QN 54 receives an output signal of inverter IV 2 . [0112] Transistors QP 55 and QN 54 are connected in series between a node N 50 and ground potential node 41 . Transistors QP 56 and QN 56 are connected in series between node N 50 and ground potential node 41 . Transistors QP 57 and QN 57 are connected in series between node N 50 and ground potential node 41 . [0113] The gate of transistor QP 55 is connected to the drain of transistor QN 56 . The gate of transistor QP 56 is connected to the drain of transistor QN 57 . The gate of transistor QP 57 is connected to the drain of transistor QN 56 . The gate of transistor QN 56 receives signal E 8 . The gate of transistor QN 57 receives an output signal of inverter IV 2 . [0114] The operation of switch circuit SW 1 will now be described. [0115] When signal ER outputted from memory control circuit 28 is at the H level, transistor QP 53 in switch circuit SW 1 is turned on and transistors QP 52 and QP 54 are turned off. Transistor QP 56 is turned on and transistors QP 55 and QP 57 are turned off. As a result, potential SHV node 42 and signal line BO are disconnected from each other. Therefore, when signal ER is at the H level, switch circuit SW 1 is turned off. [0116] On the other hand, when signal ER is at the L level, transistors QP 52 and QP 54 in switch circuit SW 1 are turned on, and transistor QP 53 is turned off. Transistors QP 55 and QP 57 are turned on and transistor QP 56 is turned off. As a result, switch circuit SW 1 is turned on to connect potential SHV node 42 to signal line BO. [0117] Since each of the other switch circuits SW 2 and SW 3 has the same configuration as that of switch circuit SW 1 , its description will not-be repeated. When signal E 5 outputted from logic gate L 2 is at the H level, switch circuit SW 2 is turned on. As a result, switch circuit SW 2 connects potential HV node 43 to signal line BO. When signal E 2 outputted from logic gate L 3 is at the H level, switch circuit SW 3 is turned on. As a result, switch circuit SW 3 connects sense amplifier circuit 22 to signal line BO. [0118] Node N 40 of second column selector 35 is connected to ground potential node N 41 . [0119] FIG. 8 is a block diagram showing the configuration of sense amplifier circuit 22 in FIG. 1 . [0120] Referring to FIG. 8 , sense amplifier 22 includes a plurality of sense amplifiers 221 to 228 . [0121] Sense amplifier 221 receives signal OUT 10 outputted from bit line control circuit 21 and signals RE, PV, and EV outputted from memory control circuit 28 , and outputs a signal OUT 20 to first multiplexer 23 . Similarly, sense amplifier 222 receives signal OUT 11 and signals RE, PV, and EV, and outputs a signal OUT 21 . Sense amplifier 223 receives signal OUT 12 and signals RE, PV, and EV, and outputs a signal OUT 22 . Sense amplifier 224 receives signal OUT 13 and signals RE, PV, and EV, and outputs a signal OUT 23 . Sense amplifier 225 receives signal OUT 14 and signals RE, PV, and EV, and outputs a signal OUT 24 . Sense amplifier 226 receives signal OUT 15 and signals RE, PV, and EV, and outputs a signal OUT 25 . Sense amplifier 227 receives signal OUT 16 and signals RE, PV, and EV, and outputs a signal OUT 26 . Sense amplifier 228 receives signal OUT 17 and signals RE, PV, and EV and outputs a signal OUT 27 . [0122] FIG. 9 is a circuit diagram showing the configuration of a sense amplifier in FIG. 8 . [0123] Referring to FIG. 9 , sense amplifier 221 includes P-channel MOS transistors QP 60 to QP 66 , N-channel MOS transistors QN 61 and QN 62 , and an inverter IV 3 . [0124] Transistors QP 60 and QP 61 are connected in series between a power supply potential node 60 and a node N 60 . The gate of transistor QP 60 is connected to ground potential node 41 . Signal RE is inputted to the gate of transistor QP 61 . Transistors QP 62 and QP 63 are connected in series between power supply potential node 60 and node N 60 . The gate of transistor QP 62 is connected to ground potential node 41 , and signal PV is inputted to the gate of transistor QP 63 . Transistors QP 64 and QP 65 are connected in series between power supply potential node 60 and node N 60 . The gate of transistor QP 64 is connected to ground potential node 41 . Signal EV is inputted to the gate of transistor QP 65 . [0125] Transistor QN 62 is connected between nodes N 60 and N 61 . Transistors QP 66 and QN 61 are connected in series between power supply potential node 60 and ground potential node 41 . The gate of transistor QP 66 and the gate of transistor QN 61 are connected to node N 61 . The gate of transistor QN 62 is connected to the drain of transistor QN 61 . Signal OUT 10 is inputted to node N 61 . [0126] An input terminal of inverter IV 3 is connected to node N 60 . [0127] Inverter IV 3 receives a signal outputted from node N 60 , inverts it, and outputs the inverted signal as signal OUT 20 . [0128] As described above, sense amplifier 221 makes the form of a single-end sense amplifier. [0129] The operation of sense amplifier 221 will now be described. [0130] With respect to the current driving force of each of transistors QP 60 , QP 62 , and QP 64 in sense amplifier 221 , the current driving force of QP 64 is the strongest, that of QP 60 is the second strongest, and that of QP 62 is the weakest. [0131] In a normal reading operation, signal RE is, activated (to the L level) and the other signals PV and EV maintain an inactive state. As a result, in response to the current driving force of transistor QP 60 , the sensitivity of the sense amplifier is determined. In a verifying operation in the writing operation, signal PV is made active (L level) and the other signals RE and EV maintain the inactive state. As a result, transistor QP 62 of which current driving force is small is connected to node N 60 , and the potential on node N 60 decreases even when a pull-out current by a memory cell via transistor QN 62 is very low. Therefore, the potential on node N 60 does not become equal to or smaller than a logic threshold value of inverter IV 3 . In other words, if the threshold value of the memory cell is not sufficiently high and the pull-out current by the memory cell via transistor QN 62 is not sufficiently suppressed, sense amplifier 221 does not recognizes the state as a “programmed state”. Therefore, in the writing operation, only in the case where data is written with reliability, sense amplifier 221 outputs signal OUT 20 of the L level. [0132] In the verifying operation during the erasing operation, signal EV becomes active (L level), and the other signals RE and PV maintain the inactive state (H level). As a result, transistor QP 64 having a large current driving force is connected to node N 60 . Therefore, the potential of node N 60 does not decreases even if the pull-out current by the memory cell via transistor QN 62 is rather large, and does not becomes equal to or lower than the logic threshold value of inverter IV 3 . That is, if the threshold value of the memory cell is not sufficiently low and the pull-out current by the memory cell via transistor QN 62 is not sufficiently obtained, the state is not regarded as an “erase state”. As a result, in the erasing operation, only in the case where data is erased with reliability, sense amplifier 221 outputs signal OUT 20 of the H level. [0133] As described above, by changing the sensitivity of the sense amplifier between the verifying operation in the writing operation and that in the erasing operation, reliability of the sense amplifier can be increased. [0134] Although sense amplifier 221 has been described by referring to FIG. 9 , since the configuration of each of the other sense amplifiers 222 to 228 is the same as that of sense amplifier 221 , its description will not be repeated. [0135] In FIG. 9 , the sense amplifier is of the single end type. However, sense amplifier of other configurations may be also employed. [0136] FIG. 10 is a circuit diagram showing the other configuration of the sense amplifier in FIG. 8 . [0137] Referring to FIG. 10 , sense amplifier 221 includes sense circuits 61 and 62 , a differential amplifier 63 , and a reference potential generating circuit 64 . [0138] Sense circuit 61 includes P-channel MOS transistors QP 70 and QP 71 and N-channel MOS transistors QN 70 to QN 72 . [0139] Transistors QP 70 and QN 72 are connected in series between power supply potential node 60 and node N 72 . The gate of transistor QP 70 is connected to ground potential node 41 . Transistors QP 71 and QN 70 are connected in series between power supply potential node 60 and ground potential node 41 . Both the gate of transistor QP 71 and the gate of transistor QN 70 are connected to a node N 72 . The gate of transistor QN 72 is connected to the drain of transistor QN 70 . Sense circuit 61 receives signal OUT 10 by node N 72 , and outputs a signal from node N 70 as a connection point of transistors QP 70 and QN 72 . [0140] Transistor QN 71 is connected between node N 72 and ground potential node 41 , and its gate is connected to power supply potential node 60 . Since the gate length of transistor QN 71 is long, only a very small current flows. As a result, transistor QN 71 has the role of adjusting the operation point of node N 70 . [0141] Since the configuration of sense circuit 62 is similar to that of sense circuit 61 except that sense circuit 62 receives a signal φB outputted from reference potential generating circuit 64 in place of signal OUT 10 , its description will not be repeated. [0142] Differential amplifier 63 includes P-channel MOS transistors QP 72 and QP 73 and N-channel MOS transistors QN 73 to QN 75 . [0143] Transistors QP 72 , QN 73 , and QN 75 are connected in series between power supply potential node 60 and ground potential node 41 . Transistors QP 73 and QN 74 are connected in series between power supply potential node 60 and the drain of transistor QN 75 . The gate of transistor QP 72 is connected to the gate of transistor QP 73 . The gate of transistor QP 73 is diode-connected. Therefore, transistors QP 72 and QP 73 construct a current mirror. The gate of transistor QN 73 receives an output signal of sense circuit 61 . The gate of transistor QN 74 receives an output signal of sense circuit 62 . The gate of transistor QN 75 is connected to power supply potential node 60 . Transistor QN 75 functions as a constant current source. Differential amplifier 63 compares an output signal of sense circuit 61 with an output signal of sense circuit 62 , and outputs the result from a node N 73 as a connection point of transistors QP 72 and QN 73 . An inverter IV 4 receives an output signal of differential amplifier 63 , inverts it, and outputs the inverted signal. An inverter IV 5 receives an output signal of inverter IV 4 , inverts it, and outputs the inverted signal as signal OUT 20 . [0144] Reference potential generating circuit 64 includes transistors QN 79 to QN 81 and reference cells RC 1 to RC 3 . [0145] Transistor QN 79 and reference cell RC 1 are connected in series between node N 72 in sense circuit 62 and ground potential node 41 . Transistor QN 80 and reference cell RC 2 are connected in series between node N 72 in sense circuit 62 and ground potential node 41 . Further, transistor QN 81 and reference cell RC 3 are connected in series between node N 72 in sense circuit 62 and ground potential node 41 . Signal RE is inputted to the gate of transistor QN 79 . Signal PV is inputted to the gate of transistor QN 80 . Signal EV is inputted to the gate of transistor QN 81 . [0146] Reference cells RC 1 to RC 3 have the same structure, material, and size as those of normal memory cells. To the gates of reference cells RC 1 to RC 3 , a reference word line RWL is commonly connected. [0147] The threshold value of reference cell RC 2 is set to be larger than that of reference cell RC 1 , and the threshold value of reference cell RC 3 is set to be smaller than that of reference cell RC 1 . For example, when the threshold value of reference cell RC 1 is set to 2.5V, the threshold value of reference cell RC 2 is set to 3.5V, and the threshold value of reference cell RC 3 is set to 1.5V. [0148] As a result, the potential of an output signal of sense circuit 62 at the time of verification in the writing operation is the highest, and that at the time of verification in the erasing operation is the lowest. Therefore, in the writing operation, only in the case where data is written with reliability, signal OUT 20 becomes L level. In the erasing operation, only when data is erased with reliability, signal OUT 20 becomes H level. [0149] Consequently, by changing the sensitivity of sense amplifier 221 between the writing operation and the erasing operation, the writing and erasing states can be checked more reliably. [0150] Although the configuration of sense amplifier 221 has been described by referring to FIG. 10 , as the configuration of each of the other sense amplifiers 222 to 228 is the same as that of sense amplifier 221 , its description will not be repeated. [0151] FIG. 11 is a block diagram showing the configuration of row decoder 29 in FIG. 1 . [0152] Referring to FIG. 11 , row decoder 29 includes a plurality of word drivers WD 0 to WVD 255 . Word driver WDq (q denotes an integer from 0 to 255) receives a signal ROWq outputted from memory control circuit 28 and signals PG, RE, PV, EV, SHGV, and HGV, and outputs an activated signal to a word line WLq. [0153] FIG. 12 is a circuit diagram showing the configuration of a word driver in FIG. 11 . [0154] Referring to FIG. 12 , word driver WD 0 includes logic gates L 10 to L 13 , switch circuits SW 4 and SW 5 , and an N-channel MOS transistor QN 82 . [0155] Word line WL 0 is connected to a potential SHGV node 71 via switch circuit SW 4 , and is connected to a potential HGV node 72 via switch circuit SW 5 . Since the configuration of each of switch circuits SW 4 and SW 5 is the same as that of switch circuit SW 1 shown in FIG. 7 , its description will not be repeated. [0156] Logic gate L 10 receives signals PG and ROW 0 and outputs a result of AND logic operation of an inversion signal of signal PG and signal ROW 0 as a signal E 10 . When signal E 10 is at the L level, switch circuit SW 4 is turned off, so that word line WL 0 and potential SHGV node 71 are disconnected from each other. On the other hand, when signal E 10 is at the H level, switch circuit SW 4 is turned on. Therefore, the potential of word line WL 0 is maintained at a potential SHGV. [0157] Logic gate L 12 receives signals RE, PV, and EV. When all of signals RE, PV, and EV are at the H level, logic gate L 12 outputs a signal of the L level. When even one of signals RE, PV, and EV is at the L level, logic gate L 12 outputs a signal of the H level. Logic gate L 13 receives an output signal of logic gate L 12 and signal ROW 0 , and outputs a result of the AND logic operation as a signal E 4 . [0158] When signal E 4 is at the L level, switch circuit SW 5 is turned off. Therefore, at this time, potential HGV node 72 and word line WL 0 are disconnected from each other. On the other hand, when signal E 4 is at the H level, switch circuit SW 5 is turned on. Therefore, potential HGV node 72 and word line WL 0 are connected to each other, and the potential of word line WL 0 is maintained at potential HGV. [0159] FIG. 13 is a block diagram showing the configuration of a memory control circuit in FIG. 1 . [0160] Referring to FIG. 13 , memory control circuit 28 includes a peripheral circuit 281 , a count circuit 282 , an SHGV detecting circuit 285 , an SHV detecting circuit 286 , an HV detecting circuit 287 , an HGV detecting circuit 288 , an SHGV oscillator 289 , an SHV oscillator 290 , an HV oscillator 291 , an HGV oscillator 292 , an SHGV charge pump 293 , an SHV charge pump 294 , an HV charge pump 295 , and an HGV charge pump 296 . [0161] Peripheral circuit 281 controls the whole semiconductor memory device 100 . Peripheral circuit 281 outputs signals PG and PV at the time of a writing operation, and outputs signals ER and EV at the time of an erasing operation. Peripheral circuit 281 receives a signal VERIFY outputted from comparator 25 . [0162] Count circuit 282 is a 4-bit counter. Each time signal PG is outputted from peripheral circuit 281 , count circuit 282 increments the count value by one, and outputs count signals CNT 0 to CNT 3 . [0163] SHGV detecting circuit 285 , SHGV oscillator 289 , and SHGV charge pump 293 construct a booster circuit. [0164] SHGV detecting circuit 285 receives a signal SHGV outputted from SHGV charge pump 293 and detects whether the potential of signal SHGV reaches a predetermined potential or not. If the potential of received signal SHGV has not reached the predetermined potential, SHGV detecting circuit 285 outputs a signal φC 1 of the H level to SHGV oscillator 289 . If the potential of received signal SHGV has reached the predetermined potential, SHGV detecting circuit 285 outputs signal φC 1 of the L level to SHGV oscillator 289 . [0165] When signal φC 1 is at the H level, SHGV oscillator 289 outputs a clock signal to boost SHGV charge pump 293 . When signal φC 1 is at the L level, SHGV oscillator 289 stops its operation. [0166] In the writing operation, SHGV charge pump 293 outputs signal SHGV having the potential boosted in response to the clock signal outputted from SHGV oscillator 289 . Signal SHGV has a gate potential in the writing operation. [0167] SHV detecting circuit 286 , SHV oscillator 290 , and SHV charge pump 294 construct a booster circuit. [0168] SHV detecting circuit 286 receives a signal SHV outputted from SHV charge pump 294 , detects whether the potential of signal SHV has reached a predetermined potential or not, and outputs a signal φC 2 . [0169] In response to signal φC 2 , SHV oscillator 290 outputs a clock signal for boosting SHV charge pump 294 . [0170] In the erasing operation, SHV charge pump 294 outputs signal SHV having the potential boosted in response to the clock signal outputted from SHV oscillator 290 . Signal SHV has the drain potential at the time of the erasing operation. [0171] HV detecting circuit 287 , HV oscillator 291 , and HV charge pump 295 construct a booster circuit. [0172] HV detecting circuit 287 receives a signal HV outputted from HV charge pump 295 , detects whether the potential of signal HV has reached a predetermined potential or not, and outputs a signal φC 3 . [0173] In response to signal φC 3 , SHV oscillator 291 outputs a clock signal for boosting HV charge pump 295 . [0174] In the writing operation, HV charge pump 295 outputs signal HV having the potential boosted in response to the clock signal outputted from HV oscillator 291 . Signal HV has the drain potential at the time of the writing operation. [0175] HGV detecting circuit 288 , HGV oscillator 292 , and HGV charge pump 296 construct a booster circuit. [0176] HGV detecting circuit 288 receives a signal HGV outputted from HGV charge pump 296 , detects whether the potential of signal HGV has reached a predetermined potential or not, and outputs a signal φC 4 . [0177] In response to signal φC 4 , HGV oscillator 292 outputs a clock signal for boosting HGV charge pump 296 . [0178] In the reading operation, HGV charge pump 296 outputs signal HGV having the potential boosted in response to the clock signal outputted from HGV oscillator 292 . Signal HGV has the gate potential at the time of the reading operation. [0179] FIG. 14 is a circuit diagram showing the configuration of an SHV detecting circuit in FIG. 13 . [0180] Referring to FIG. 14 , SHV detecting circuit 286 includes P-channel MOS transistors QP 75 and QP 76 , N-channel MOS transistors QN 85 and QN 86 , resistive elements R 1 to R 6 , transfer gates T 1 to T 4 , inverters IV 10 to IV 13 , and operational amplifiers OP 1 and OP 2 . [0181] Transistor QP 75 and resistive element R 6 are connected in series between power supply potential node 60 and ground potential node 41 . An output terminal of operational amplifier OP 1 is connected to the gate of transistor QP 75 . A reference potential Vref is inputted to an inversion input terminal of operational amplifier OP 1 . A non-inversion input terminal of operational amplifier OP 1 is connected to the drain of transistor QP 75 . [0182] Transistors QP 76 and QN 85 are connected in series between power supply potential node 60 and ground potential node 41 . The gate of transistor QP 76 is connected to an output terminal of operational amplifier OP 1 . Transistor QN 85 is diode-connected. [0183] Resistive elements R 1 to R 5 and transistor QN 86 are connected in series. To a terminal which is not connected to resistive element R 2 , as one of two terminals of resistive element R 1 , signal SHV outputted from SHV charge pump 294 is inputted. The drain of transistor QN 86 is connected to resistive element R 5 , and the gate of transistor QN 86 is connected to the gate of transistor QN 85 . The source of transistor QN 86 is connected to ground potential node 41 . [0184] Each of transfer gates T 1 to T 4 is constructed by an N-channel MOS transistor and a P-channel MOS transistor. [0185] Transfer gate T 1 and resistive element R 1 are connected in parallel. An output signal of inverter IV 10 is inputted to the gate of the P-channel MOS transistor in transfer gate T 1 . To inverter IV 10 and the gate of the N-channel MOS transistor, count signal CNT 3 outputted from count circuit 282 is inputted. Transfer gate T 2 and resistive element R 2 are connected in parallel. An output signal of inverter IV 11 is inputted to the gate of the P-channel MOS transistor in transfer gate T 2 . To inverter IV 11 and the gate of the N-channel MOS transistor, count signal CNT 2 outputted from count circuit 282 is inputted. Transfer gate T 3 and resistive element R 3 are connected in parallel. An output signal of inverter IV 12 is inputted to the gate of the P-channel MOS transistor in transfer gate T 3 . Count value CNT 1 outputted from count circuit 282 is inputted to inverter IV 12 and the gate of the N-channel MOS transistor. Transfer gate T 4 and resistive element R 4 are connected in parallel. An output signal of inverter IV 13 is inputted to the gate of the P-channel MOS transistor in transfer gate T 4 . To inverter IV 13 and the gate of the N-channel MOS transistor, count signal CNT 0 outputted from count circuit 282 is inputted. [0186] The inversion input terminal of operational amplifier OP 2 is connected to a node N 80 as a connection point of resistive element R 5 and transistor QN 86 . Reference potential Vref is inputted to the non-inversion input terminal of operational amplifier OP 2 . When the potential inputted to the inversion input terminal is higher than reference potential Vref inputted to the non-inversion input terminal, operational amplifier OP 2 outputs signal φC 2 of the L level. When the potential inputted to the inversion input terminal is lower than reference potential Vref inputted to the non-inversion input terminal, operational amplifier OP 2 outputs signal φC 2 of the H level. [0187] The operation of SHV detecting circuit 286 will now be described. [0188] When the potential inputted to the non-inversion input terminal of operational amplifier OP 1 is lower than reference potential Vref inputted to the inversion input terminal, operational amplifier OP 1 outputs an L-level signal. At this time, therefore, transistor QP 75 is turned on. As a result, the potential inputted to the non-inversion input terminal of operational amplifier OP 1 increases. When the potential of the non-inversion input terminal becomes higher than reference potential Vref, an output signal of operational amplifier OP 1 becomes H level. Therefore, transistor QP 75 is turned off. As a result, the potential of the non-inversion input terminal decreases. Since the potential of the non-inversion input terminal becomes constant, a current I 1 flowing in resistive element R 6 becomes a constant value Vref/R 6 . [0189] Since an output signal of operational amplifier OP 1 is also inputted to the gate of transistor QP 76 , if the size of transistor QP 75 and that of transistor QP 76 are set to the same, a current I 2 flowing in transistor QN 85 also becomes constant value Vref/R 6 . Further, if the size of transistor QN 85 and that of transistor QN 86 are set to the same, a gate-source potential of transistor QN 85 and that of transistor QN 86 are the same. Consequently, a current flowing in transistor QN 86 becomes constant value Vref/R 6 . That is, the current flowing in node N 80 becomes constant. All of transistors QP 75 , QP 76 , QN 85 , and QN 86 operate in a saturation region. [0190] Therefore, the potential inputted to the inversion input terminal of operational amplifier OP 2 is determined by the potential of signal SHV and a resistance value used between nodes N 81 and N 80 . The resistance value used between nodes N 81 and N 80 is determined on the basis of the count value of count circuit 282 , concretely, determined on the basis of count signals CNT 0 to CNT 3 outputted from count circuit 282 . [0191] Since the circuit configuration of each of SHGV detecting circuit 285 , HV detecting circuit 287 , and HGV detecting circuit 288 is the same as that of SHV detecting circuit 286 , its description will not be repeated. [0192] Referring again to FIG. 1 , when signal RE is received from memory control circuit 28 , first multiplexer 23 outputs signal OUT 2 received from sense amplifier circuit 22 to output buffer 24 . When signal PV or EV is received from memory control circuit 28 , first multiplexer 23 outputs signal OUT 2 received from sense amplifier circuit 22 to comparator 25 . [0193] Input buffer 27 receives external data signals DQ 0 to DQ 7 inputted from the outside and outputs internal data signals DIN 0 to DIN 7 . [0194] Further, input buffer 27 outputs signal IN 0 to IN 7 on the basis of external data signals DQ 0 to DQ 7 . [0195] Second multiplexer 26 receives signal PV from memory control circuit 28 at the time of a writing operation and outputs signals IN 0 to IN 7 . Second multiplexer 26 receives signal EV from memory control circuit 28 at the time of an erasing operation, and outputs H-level signals HIN 0 to HIN 7 . [0196] At the time of a writing operation, comparator 25 compares signal OUT 2 (OUT 20 to OUT 27 ) outputted from first multiplexer 23 with signals IN 0 to IN 7 outputted from second multiplexer 26 , respectively and, when signal OUT 2 coincides with signals IN 0 to IN 7 , outputs signal VERIFY of the H level to memory control circuit 28 . At the time of an erasing operation, comparator 25 compares signal OUT 2 outputted from first multiplexer 23 with signals HIN 0 to HIN 7 of the H level outputted from second multiplexer 26 and, when all of signals OUT 2 are at the H level, outputs signal VERIFY of the H level to memory control circuit 28 . [0197] The writing operation of semiconductor memory device 100 having the above circuit configuration will be described. [0198] FIG. 15 is a flowchart showing the writing operation of the semiconductor memory device in the first embodiment of the present invention. [0199] A case of writing data into storing region 9 R in FIG. 30 in an arbitrary memory cell in memory cell array 20 in semiconductor memory device 100 will now be described. [0200] Referring to FIG. 15 , first, the count value of count circuit 282 in memory control circuit 28 is reset by a reset signal RESET outputted from peripheral circuit 281 . Reset signal RESET is always set to the L level. At this time, therefore, all of count signals CNT 0 to CNT 3 outputted from count circuit 282 become L level. All of signals PG, PV, ER, and EV outputted from peripheral circuit 281 are at the H level. [0201] After that, in order to apply a write voltage to a memory cell, memory control circuit 28 activates signal PG outputted from peripheral circuit 281 to the L level. The other signals PV, ER, and EV outputted from peripheral circuit 281 maintain the H level. At this time, HV detecting circuit 287 , HV oscillator 291 , and HV charge pump 295 operate. As a result, HV charge pump 295 outputs drain voltage HV to be applied to a memory cell. [0202] Similarly, by the activation of signal PG, SHGV detecting circuit 285 , SHGV oscillator 289 , and SHGV charge pump 293 operate. As a result, SHGV charge pump 293 outputs gate voltage SHGV to be applied to a memory cell (step S 1 ). [0203] Subsequently, after elapse of a predetermined period since-a write voltage is applied, semiconductor memory device 100 performs a verifying operation (step S 2 ). [0204] The verifying operation is an operation for determining whether data is normally written in a memory cell or not after applying the write voltage to the memory cell. [0205] When the verifying operation is performed, signal PG outputted from peripheral circuit 281 becomes H level, and signal PV is activated to the L level. As a result, a predetermined voltage is applied to the gate and source of the memory cell, and data written in the memory cell is read out by sense amplifier circuit 22 . The read data is inputted as signal OUT 2 to comparator 25 via first multiplexer 23 . On the other hand, comparator 25 receives signal IN as data information written into the memory cell from second multiplexer 26 . [0206] Comparator 25 compares signal OUT 2 with signal IN, and detects whether 8-bit digital data of signal OUT 2 coincides with 8-bit digital data of signal IN or not. In the case where data of signal OUT 2 and data of signal IN coincide with each other (step S 3 ), it is determined that data to be written into the memory cell is normally written, that is, charges accumulated in storing region 9 R in the memory cell are sufficient, and the writing operation is finished (step S 4 ). [0207] On the other hand, in the case where data of signal OUT 2 and data of signal IN do not coincide with each other (step S 3 ), comparator 25 determines that charges accumulated in storing region 9 R in the memory cell are insufficient. [0208] Returning again to step S 2 , semiconductor memory device 100 repeats application of the write voltage until a predetermined amount of charges is accumulated in storing region 9 R in the memory cell. [0209] With respect to the erasing operation as well, similarly, after applying an erase voltage, the verifying operation is performed, and application of the erase voltage is repeated until charges in storing region 9 R in the memory cell are discharged. [0210] FIG. 16 is a timing chart of the writing operation in the semiconductor memory device in the first embodiment of the present invention. [0211] It is assumed that the writing operation of the semiconductor memory device in FIG. 16 is performed under the same conditions as those for the writing-operation in FIG. 15 . Vth in FIG. 16 indicates a written threshold voltage of the memory cell. B indicates a voltage of the semiconductor substrate of the memory cell, S indicates a voltage applied to diffusion bit line 7 A of the memory cell, D denotes a voltage (voltage of signal HV) applied to diffusion bit line 7 B of the memory cell, and G denotes a voltage (voltage of signal SHGV) applied to control gate 11 of the memory cell. [0212] Referring to FIG. 16 , signal PG is activated to the L level at time t 1 , and semiconductor memory device 100 performs application of the write voltage of the first time. The other signals PV, ER, and EV outputted from peripheral circuit 281 at this time maintain the H level. At this time, HV detecting circuit 287 , HV oscillator 291 , and HV charge pump 295 operate. As a result, HV charge pump 295 outputs drain voltage HV to be applied to the memory cell. Signal HV is maintained at a constant voltage VD 1 . [0213] Similarly, by the activation of signal PG, SHGV detecting circuit 285 , SHGV oscillator 289 , and SHGV charge pump 293 operate. As a result, SHGV charge pump 293 outputs signal HGV to be applied to the gate of the memory cell. At this time, signal HGV is maintained at a constant voltage VG 1 . [0214] At time t 2 after the write voltage is applied for a predetermined period, signal PG becomes H level and signal PV becomes L level. As a result, semiconductor memory device 100 starts the verifying operation. [0215] Assuming now that when the-threshold voltage of the memory cell becomes Vth 1 , sufficient charges are accumulated in storing region 9 R in the memory cell. Threshold voltage Vth of the memory cell at time t 2 is lower than Vth 1 . Therefore, comparator 25 determines that charges accumulated in storing region 9 R are insufficient. As a result, signal PG becomes L level at time t 3 , and the write voltage is applied again. [0216] Subsequently, at time t 4 , a verifying operation is performed. Since the operating method is the same as that at time t 2 , its description will not be repeated. [0217] By the above operations, until threshold value Vth of the memory cell to which the writing operation is performed becomes Vth 1 , semiconductor memory device 100 repeats application of the write voltage and the verifying operation. When threshold value Vth of the memory cell exceeds Vth 1 as a result of the verifying operation at time t 5 , comparator 25 outputs pulse signal VERIFY of the H level. Memory control circuit 28 receives signal VERIFY of the H level and finishes the writing operation at time t 6 . [0218] The case of the erasing operation is similar to the above. In the case of the erasing operation, whether the threshold value of the memory cell becomes equal to or lower than a predetermined voltage (for example, 1.5V or less) is determined in the verifying operation. If the threshold is not equal to or lower than the predetermined voltage, the erasing operation is repeated. [0219] By the above operation, semiconductor memory device 100 in the first embodiment repeats application of the write voltage and the verifying operation at the time of the writing operation. As a result, charges are prevented from being excessively injected into the memory cell. With respect to the erasing operation, similar operations are performed. [0220] FIG. 17 is a timing chart showing the operations of circuits in the semiconductor memory device at the time of the writing operation. [0221] In FIG. 17 , a case of writing data “01110111” into storing region 9 R in a memory cell MC 1 in FIG. 2 with respect to memory blocks MB [ 1 , 1 ], MB [ 1 , 9 ], MB [ 1 , 17 ], MB [ 1 , 25 ], MB [ 1 , 33 ], MB [ 1 , 41 ], MB [ 1 , 49 ], and MB [ 1 , 57 ] in semiconductor memory device 100 shown in FIG. 1 will be described. Concretely, data “0” is stored in memory cell MC 1 in each of memory blocks MB [ 1 , 1 ] and MB [ 1 , 33 ], and data “1” is stored in memory cell MC 1 of each of the other memory blocks MB. “0” denotes a state where the threshold value is high, and “1” indicates a state where the threshold value is low. [0222] Referring to FIG. 17 , first, signal PG outputted from peripheral circuit 281 at time t 11 is activated to the L level. Among signals CS 0 to CS 7 to be inputted to core circuits 211 to 218 in bit line control circuit 21 , signals CS 0 and CS 1 become H level. The other signals CS 2 to CS 7 remain at the L level. [0223] Among signals BS 0 to BS 15 to be inputted to core circuits 211 to 218 , signals BS 0 and BS 1 become L level, and the other signals BS 2 to BS 15 maintain the H level. [0224] As a result, transistors QN 30 and QN 31 in first column selectors 31 to 34 in core circuits 211 to 218 are turned on. Transistors QP 40 and QN 41 in second column selector 35 are also turned on. Consequently, in memory block MB [ 1 , 1 ], main bit line MBL 2 is connected to node N 40 in second column selector 35 , and main bit line MB 1 is connected to node N 41 . Similarly, in each memory block [ 1 , 8 J+1] (J: integer from 0 to 7), a main bit line MBL ( 4 ×( 8 J+1)−2) is connected to node N 40 in second column selector 35 in each core circuit, and a main bit line MBL( 4 ×( 8 J+1)−3) is connected to node N 41 . [0225] Attention is now paid to potential control circuit 36 in core circuit 211 . At time t 11 , signal DIN 0 to be written into memory cell MC 1 in memory block MB [ 1 , 1 ] becomes at the L level (corresponding to data “0”), so that switch circuit SW 2 is turned on. As a result, the potential on main bit line MBL 1 becomes potential HV. On the other hand, main bit line MBL 2 is connected to ground potential node 41 . [0226] Similarly, the potential on main bit line MBL 129 in memory block [ 1 , 33 ] becomes potential HV, and main bit line MBL 2 is connected to ground potential node 41 . [0227] In the other memory block MB [ 1 , 8 J+1], internal data signal DIN to be inputted to corresponding potential control circuit 36 becomes H level (corresponding to data “1”). As a result, all of signals E 8 , E 5 , and E 2 in potential control circuit 36 become L level, and transistor QN 51 is turned on. Therefore, both of main bit lines MBL ( 4 ×( 8 J+1)−2) and MBL ( 4 ×( 8 J+1)−3) in memory block MB [ 1 , 8 J+1] become L level. [0228] By the above operations, main bit line MBL 1 in memory block MB [ 1 , 1 ] is maintained at potential HV (H level), and main bit line MBL 2 becomes L level. Main bit line MBL 129 in memory block MB [ 1 , 33 ] is maintained at potential HV (H level), and main bit line MBL 2 becomes L:level. [0229] After that, at time t 12 , among signal lines S 1 to S 4 in memory block MB, signal lines S 2 and S 3 become H level. At this time, signal lines S 1 and S 4 maintain the L level. Therefore, transistors QN 3 and QN 5 are turned on. As a result, in memory block MB[ 1 , 1 ], main bit line MBL 1 is connected to bit line BL 2 , and main bit line MBL 2 is connected to bit line BL 1 . Similarly, in memory block MB [ 1 , 33 ], main bit line MBL 129 is connected to bit line BL 2 , and main bit line MBL 130 is connected to bit line. BL 1 . As a result, bit line BL 2 is maintained at potential HV (H level), and bit line BL 1 is maintained at the ground potential (La level). [0230] Subsequently, word line WL 0 is activated to the H level at time t 13 . As a result, operation of writing data to storing region 9 R in memory cell MC 1 in memory blocks MB [ 1 , 1 ] and MB [ 1 , 33 ] is performed, and charges are accumulated in storing region 9 R. [0231] By the above operations, a write voltage is applied to a designated memory cell, and writing operation is performed. [0232] At time t 14 , signal PG becomes H level. At this time, word line WL 0 becomes L level, and the writing operation is finished. Since signal PG becomes H level, supply of potential HV to main bit line MBL is stopped and, after completion of the writing operation, main bit lines MBL 1 and MBL 129 become L level. As a result, bit line BL 2 also becomes L level. After main bit lines MBL 1 and MBL 129 become L level, signals BS 0 and BS 1 become H level. [0233] At time t 21 , signal PV becomes L level. Therefore, semiconductor memory device 100 performs a verifying operation. [0234] At the time of the verifying operation, signals BS 0 and BS 1 in the core circuit maintain the H level, and signals BS 2 and BS 3 become L level. Therefore, in memory block MB [ 1 , 1 ], transistors QN 40 and QP 41 in second column selector 35 are turned on. As a result, main bit line MBL 1 is connected to node N 40 , and main bit line MBL 2 is connected to node N 41 . [0235] Since signals RE and EV are at the H level and signal PV is at the L level, signal E 2 outputted from logic gate L 3 in potential control circuit 36 becomes H level. As a result, switch circuit SW 3 is turned on, and main bit line MBL 2 (corresponding to signal B 2 ) is maintained at the read potential (about 2 V). On the other hand, main bit line MBL 1 is connected to ground potential node 41 , and the potential of main bit line MBL 1 (corresponding to signal B 1 ) maintains the ground potential. [0236] Also in other memory block MB [ 1 , 8 J+1], similarly, main bit line MBL ( 4 × 8 J+1)−2) (corresponding to signal B 2 ) is maintained at the reading potential (about 2V), and main bit line MBL ( 4 ×( 8 J+1)−3) (corresponding to signal B 1 ) is maintained at the ground potential. [0237] As a result, bit line BL 1 in each memory block MB [ 1 , 8 J+1] is maintained at the read potential, and bit line BL 2 is maintained at the ground potential. [0238] After that, when word line WL 0 is activated to the H level (about 3V in the reading operation) at time t 22 , the operation of reading data from storing region 9 R in memory cell MC 1 in each memory block MB [ 1 , 8 J+1] is started. [0239] As a result, sense amplifier circuit 22 reads data in storing region 9 R in memory cell MC 1 in each memory block MB [ 1 , 8 J+1], and outputs the result as signal OUT 2 to comparator 25 via first multiplexer 23 . [0240] At time t 23 , comparator 25 compares the result of signal OUT 2 with signal IN as storage information outputted from second multiplexer 26 . [0241] When signals OUT 2 and IN do not coincide with each other as a result of comparison, that is, when storage of charges is insufficient for even one of data in storing region 9 R in memory cell MC 1 in memory block MB [ 1 , 8 J+1], comparator 25 outputs signal VERIFY of the L level. On the other hand, when signals OUT 2 and IN coincide with each other, comparator 25 outputs signal VERIFY at the H level. [0242] When signal PV becomes H level at time t 24 , potential control circuit 36 in the core circuit stops supply of the read potential to main bit line MBL. Word line WL 0 becomes L level. Therefore, the verifying operation is finished. [0243] All of signals S 1 to S 4 become L level at time t 25 after completion of the verifying operation, and all of signals CS 0 to CS 7 also become L level. All of signals BS 0 to BS 15 become H level. [0244] As a result of the verifying operation, when signal VERIFY is at the L level, the writing operation is performed again after time t 25 . As the operation at that time, the operations performed at times t 11 to t 14 are repeated. After completion of the writing operation, the verifying operation is performed again and the writing operation is repeated until signal VERIFY becomes H level. [0245] As a result of the verifying operation, when signal VERIFY is at the H level, the semiconductor memory device finishes the writing operation. [0246] By the above operation, the data “01110111” is written in storing region 9 R in memory cell MC 1 in FIG. 2 with respect to memory blocks MB [ 1 , 1 ], MB [ 1 , 9 ], MB [ 1 , 17 ], MB [ 1 , 25 ], MB [ 1 , 33 ], MB [ 1 , 41 ], MB [ 1 , 49 ] and MB [ 1 , 57 ] in semiconductor memory device 100 . [0247] The erasing operation will now be described. [0248] FIG. 18 is a timing chart showing the operations of circuits in the semiconductor memory device at the time of the erasing operation. [0249] In FIG. 18 , a case of erasing all of data in storing region 9 R in memory cell MC 1 in FIG. 2 with respect to memory blocks MB [ 1 , 1 ], MB [ 1 , 9 ], MB [ 1 , 17 ], MB [ 1 , 25 ], MB [ 1 , 33 ], MB [ 1 , 41 ], MB [ 1 , 49 ], and MB [ 1 , 57 ] in semiconductor memory device 100 shown in FIG. 1 will be described. Concretely, data “1” is stored in memory cell MC 1 in each of memory blocks MB. In this case, “0” denotes a state where the threshold value is high, and “1” indicates a state where the threshold value is low. [0250] Referring to FIG. 18 , at time t 31 , signal ER outputted from peripheral circuit 281 is activated to the L level. [0251] Among signals CS 0 to CS 7 to be inputted to core circuits 211 to 218 in bit line control circuit 21 , signals CS 0 and CS 1 become H level. The other signals CS 2 to CS 7 remain at the L level. [0252] Among signals BS 0 to BS 15 to be inputted to core circuits 211 to 218 , signals BS 0 and BS 1 become L level, and the other signals BS 2 to BS 15 maintain the H level. [0253] As a result, transistors QN 30 and QN 31 in first column selectors 31 to 34 in core circuits 211 to 218 are turned on. Transistors QP 40 and QN 41 in second column selector 35 are also turned on. Consequently, in memory block MB [ 1 , 1 ], main bit line MBL 2 is connected to node N 40 in second column selector 35 , and main bit line MBL 1 is connected to node N 41 . Similarly, in each memory block [ 1 , 8 J+1] (J: integer from 0 to 7), main bit line MBL ( 4 ×( 8 J+1)−2) is connected to node N 40 in second column selector 35 in each core circuit, and main bit line MBL ( 4 ×( 8 J+1)−3) is connected to node N 41 . [0254] Attention is now paid to potential control circuit 36 in core circuit 211 . At time t 31 , signal ER becomes at the L level, so that switch circuit SW 1 is turned on. As a result, the potential on main bit line MBL 1 becomes potential SHV. On the other hand, main bit line MBL 2 is connected to ground potential node 41 . [0255] Similarly, also in each memory block MB [ 1 , 8 J+1] (J: integer from 0 to 7), main bit line MBL ( 4 × 8 J+1)−2) is connected to ground potential node 41 , and the potential on main bit line MBL ( 4 ×( 8 J+1)−3) is maintained at potential SHV. [0256] After that, at time t 32 , among signal lines S 1 to S 4 in memory block MB, only signal line S 2 becomes H level. Therefore, transistor QN 2 is turned on. As a result, in memory block MB [ 1 , 1 ], main bit line MBL 1 is connected to bit line BL 2 . On the other hand, the other main bit lines MBL 2 to MBL 4 are not connected to any bit lines BL. [0257] As a result, potential SHV is applied to the drain of each of all of memory cells connected to bit line BL 2 , and the source becomes a floating potential. Therefore, in all of memory cells connected to bit line BL 2 , the erasing operation is started. For example, in the case where the number of memory cells per column in each memory block MB is 32 , in memory block MB [ 1 , 1 ], in storing regions 9 R of the 32 memory cells connected between bit lines BL 2 and BL 1 , and storing regions 9 L in the 32 memory cells connected between bit lines BL 2 and BL 3 , erasing operation of 64 bits is performed at once. Similarly, in each memory block [ 1 , 8 J+1] (J: integer from 0 to 7), an operation of erasing 64 bits is performed. In the whole semiconductor memory device, the operation of erasing data of 512 bits is performed after time t 32 . [0258] At time t 33 , signal ER becomes H level. At this time, supply of potential SHV to main bit line MBL ( 4 ×( 8 J+1)−3) is stopped, and bit line MBL ( 4 ×( 8 J+1)−3) becomes L level after the erasing operation. Accordingly, bit line BL 2 becomes L level. After main bit line MBL ( 4 ×( 8 J+1)−3) becomes L level, signals BS 0 and BS 1 become H level. [0259] At time t 41 , signal EV becomes L level, so that semiconductor memory device 100 performs the verifying operation. [0260] In the verifying operation, signals BS 0 and BS 1 in the core circuit maintain the H level, and signals BS 2 and BS 3 become L level. Therefore, in memory block MB [ 1 , 1 ], transistors QN 40 and QP 41 in second column selector 35 are turned on. As a result, main bit line MBL 1 is connected to node N 40 , and main bit line MBL 2 is connected to node N 41 . [0261] At this time, since signals RE and PV are at the H level and signal EV is at the L level, signal E 2 outputted from logic gate L 3 in potential control circuit 36 becomes H level. As a result, switch circuit SW 3 is turned on, and main bit line MBL 2 (corresponding to signal B 2 ) is connected to sense amplifier circuit 22 and is maintained at read potential (about 2V) by sense amplifier circuit 22 . On the other hand, main bit line MBL 1 is connected to ground potential node 41 , and the potential of main bit line MBL 1 (corresponding to signal B 1 ) maintains the ground potential. [0262] Also in other memory block M [ 1 , 8 J+1], similarly, main bit line MBL ( 4 ×( 8 J+1)−2) (corresponding to signal B 2 ) is maintained at the read potential (about 2V), and main bit line MBL ( 4 ×( 8 J+1)−3) (corresponding to signal B 1 ) is maintained at the ground potential. [0263] As a result, bit line BL 1 in each memory block MB [ 1 , 8 J+1] is maintained at the read potential, and bit line BL 2 is maintained at the ground potential. [0264] When word line WL 0 is activated to the H level (about 3V at the time of the reading operation) at time t 42 , the operation of reading data in storing region 9 R in memory cell MC 1 in each memory block MB [ 1 , 8 J+1] is started. [0265] As a result, sense amplifier circuit 22 reads data in storing region 9 R in memory cell MC 1 in each memory block MB [ 1 , 8 J+1] and outputs the result as signal OUT 2 to comparator 25 via first multiplexer 23 . [0266] At time t 43 , comparator 25 compares the result of signal OUT 2 with a signal HIN outputted from second multiplexer 26 . [0267] As a result of the comparison, if signals OUT 2 and HIN do not coincide with each other, that is, when accumulation of charges for even one of data in storing region 9 R in memory cell MC 1 in each memory block MB [ 1 , 8 J+1] is insufficient, comparator 25 outputs signal VERIFY of-the L level. On the other hand, when signals OUT 2 and HIN coincide with each other, comparator 25 outputs signal VERIFY of the H level. [0268] When signal EV becomes H level at time t 24 , potential control circuit 36 in the core circuit stops supply of the read potential to main bit line MBL. Word line WL 0 becomes L level. [0269] At time t 45 after completion of the verifying operation, all of signals S 1 to S 4 become L level, and all of signals CS 0 to CS 7 become L level. All of signals BS 0 to BS 15 become H level. [0270] When signal VERIFY is at the L level as a result of the verifying operation, after time t 45 , the erasing operation is carried out again. The operation at this time is repetition of the operation performed at time t 31 to t 33 . After completion of the erasing operation, the verifying operation is performed again, and the erasing operation is repeated until signal VERIFY becomes H level. [0271] When signal VERIFY is at the H level as a result of the verifying operation, the semiconductor memory device finishes the erasing operation. [0272] The amount which can be verified simultaneously is one memory cell per memory block MB, that is, eight bits in the whole memory cell array. Therefore, the semiconductor memory device performs similar verifying operation in 64 cycles while changing a word line to be activated and a bit line BL to be activated. [0273] After performing the verifying operation on all of memory cells, the verifying operation is finished. [0274] By the above operation, semiconductor memory device 100 in the first embodiment repeats application of the write voltage and the verifying operation at the time of the writing operation. As a result, charges can be prevented from being excessively injected to a memory cell. Second Embodiment [0275] In the first embodiment, the voltage applied to a memory cell in the writing operation is set to be constant. However, each time the writing operation is repeated, the voltage to be applied to a memory cell can be changed. [0276] FIG. 19 is a flowchart showing the writing operation of a semiconductor memory device in the second embodiment of the present invention. [0277] In a manner similar to FIG. 15 , a case of writing data into storing region 9 R in FIG. 30 in an arbitrary memory cell in memory cell array 20 in semiconductor memory device 100 will be described. [0278] Referring to FIG. 19 , first, the count value of count circuit 282 in memory control circuit 28 is reset by reset signal RESET outputted from peripheral circuit 281 (step S 1 ). All of count signals CNT 0 to CNT 3 outputted from count circuit 282 therefore become L level at this time. All of signals PG, PV, ER, and EV outputted from peripheral circuit 281 are at the H level. [0279] After that, to apply the write voltage to a memory cell, memory control circuit 28 activates signal PG outputted from peripheral circuit 281 to the L level. At this time, other signals PV, ER, and EV outputted from peripheral circuit 281 maintain the H level, and HV detecting circuit 287 , HV oscillator 291 , and HV charge pump 295 operate. As a result, HV charge pump 295 outputs drain voltage HV to be applied to a memory cell. [0280] Similarly, by activation of signal PG, SHGV detecting circuit 285 , SHGV oscillator 289 , and SHGV charge pump 293 operate. As a result, SHGV charge pump 293 outputs gate voltage SHGV to be applied to a memory cell (step S 2 ). [0281] Subsequently, after elapse of a predetermined period since the write voltage is applied, semiconductor memory device 100 performs the verifying operation (step S 3 ). [0282] When the verifying operation is performed, signal PG outputted from peripheral circuit 281 becomes H level, and signal PV is activated to the L level. As a result, a predetermined voltage is applied to the gate and source of a memory cell, and data written in the memory cell is read by sense amplifier circuit 22 . The read data is inputted as signal OUT 2 to comparator 25 via first multiplexer 23 . On the other hand, comparator 25 receives signal IN as data information written into the memory cell from second multiplexer 26 . [0283] Comparator 25 compares signal OUT 2 with signal IN. When 8-bit digital information of signal OUT 2 and 8-bit digital information of signal IN coincide with each other (step S 4 ), it is determined that data to be written into a memory cell has been normally written, that is, charges accumulated in storing region 9 R in the memory cell are sufficient, and the writing operation is finished. [0284] On the other hand, when signals OUT 2 and IN do not coincide with each other (step S 4 ), it is determined that charges accumulated in storing region 9 R in the memory cell are insufficient, and count circuit 282 counts the number of write voltage applying times (step S 5 ). After counting, the program returns again to step S 2 , and the writing operation is performed. [0285] By the above operation, semiconductor memory device 100 applies the write voltage until a predetermined amount of charges is accumulated in storing region 9 R in the memory cell. [0286] Since the erasing operation is performed in a manner similar to the writing operation, its description will not be repeated. [0287] FIG. 20 is a timing chart of the writing operation in the semiconductor memory device in the second embodiment of the present invention. [0288] It is assumed that the writing operation of the semiconductor memory device in FIG. 20 is performed under the same conditions as those for the writing operation in FIG. 19 . Vth, B, D, and G in FIG. 20 are the same as those in FIG. 16 , so that their description will not be repeated. [0289] Referring to FIG. 20 , at time t 1 , semiconductor memory device 100 performs application of the write voltage of the first time. At this time, the other signals PV, ER, and EV outputted from peripheral circuit 281 maintain the H level, and HV detecting circuit 287 , HV oscillator 291 , and HV charge pump 295 operate. As a result, HV charge pump 295 outputs drain voltage HV to be applied to the memory cell. [0290] At this time, all of count signals CNT 0 to CNT 3 outputted from count circuit 282 are at the L level. Since all of transfer gates T 1 to T 4 in HV detecting circuit 287 are turned off, resistive elements R 1 to R 5 are connected in series between nodes N 80 and N 81 in HV detecting circuit 287 . The potential of signal HV outputted from HV charge pump 295 is divided by resistive elements R 1 to R 5 and transistor QN 86 . The divided potential is outputted from node N 80 to operational amplifier OP 2 . At this time, operational amplifier OP 2 outputs signal φC 2 of the H level until the voltage of a signal outputted from node N 80 becomes equal to reference potential Vref. When the voltage of the output signal from node N 80 becomes larger than reference potential Vref, operational amplifier OP 2 outputs signal φC 2 of the L level. By signal φC 2 , the operation of HV oscillator 291 is controlled and, as a result, HV charge pump 295 outputs signal HV to the drain of the memory cell. At this time, signal HV is maintained to constant voltage VD 1 . [0291] Similarly, by the activation of signal PG, SHGV detecting circuit 285 , SHGV oscillator 289 , and SHGV charge pump 293 operate. As a result, SHGV charge pump 293 outputs gate voltage SHGV to be applied to the memory cell. At this time, signal SHGV is maintained at constant voltage VG 1 . [0292] At time t 2 after the write voltage is applied for a predetermined period, signal PG becomes H level and signal PV becomes L level. As a result, semiconductor memory device 100 starts the verifying operation. Assuming now that when the threshold voltage of a memory cell becomes Vth 1 , sufficient charges are accumulated in storing region 9 R in the memory cell. Threshold voltage Vth of the memory cell at time t 2 is lower than Vth 1 . Therefore, comparator 25 determines that charges accumulated in storing region 9 R are insufficient. As a result, signal PG becomes L level at time t 3 , and the write voltage is applied again. [0293] At the time of the verifying operation from time t 2 to t 3 , the count number of count circuit 282 is set to “1”. Therefore, count signal CNT 0 becomes H level. [0294] As a result, transfer gate T 4 in HV detecting circuit 287 is turned on. Therefore, a voltage outputted from node N 80 in HV detecting circuit 287 becomes equal to the potential obtained by dividing the potential of signal HV by resistive elements R 1 to R 3 , and R 5 , and transistor QN 86 . Even in the case where the potential of the signal outputted from node N 80 is lower than that at time t 1 , HV detecting circuit 287 outputs signal φC 3 of the L level. [0295] Consequently, voltage VD 2 of signal HV outputted from HV charge pump 295 at time t 2 is lower than voltage DV 1 of signal HV at time t 1 . [0296] For the same reason, voltage VG 2 of signal HGV outputted from HGV charge pump 296 becomes lower than voltage VD 1 of signal HV at time t 1 . [0297] Subsequently, at time t 4 , a verifying operation is performed. Since the operating method is the same as that at time t 2 , its description will not be repeated. [0298] By the above operations, until threshold value Vth of the memory cell on which the writing operation is performed becomes Vth 1 , semiconductor memory device 100 repeats application of the write voltage and the verifying operation. Each time the number of application times of the write voltage increases, the voltage to be applied decreases. When threshold value Vth of the memory cell exceeds Vth 1 as a result of the verifying operation at time t 5 , comparator 25 outputs pulse signal VERIFY of the H level. Memory control circuit 28 receives signal VERIFY of the H level and finishes the writing operation at time t 6 . [0299] By the above operation, semiconductor memory device 100 in the first embodiment repeats application of the write voltage and the verifying operation at the time of the writing operation. As a result, charges are prevented from being excessively injected into the memory cell. Further, by decreasing the write voltage to be applied each time the number of application times of the write voltage increases, the writing operation is prevented from being excessively performed on a memory cell. [0300] With respect to the erasing operation, operations are performed in a manner similar to the writing operation, so that the description will not be repeated. At the time of the erasing operation, drain voltage become SHV and the gate voltage becomes 0V. [0301] FIG. 21 is a timing chart showing the operations of circuits in the semiconductor memory device at ;he time of the writing operation. [0302] In FIG. 21 , in a manner similar to FIG. 17 , a case of writing data “01110111” into storing region 9 R in memory cell MC 1 with respect to memory blocks MB [ 1 , 1 ], MB [ 1 , 9 ], MB [ 1 , 17 ], MB [ 1 , 25 ], MB [ 1 , 33 ], MB [ 1 , 41 ], MB [ 1 , 49 ], and MB [ 1 , 57 ] in semiconductor memory device 100 will be described. [0303] Referring to FIG. 21 , when signal PG is activated to the L level at time t 11 , signal RESET also becomes L level. As a result, count circuit 282 is reset. Therefore, all of signals CNT 0 to CNT 3 outputted from count circuit 282 become L level. After that, signal RESET becomes H level during the writing operation and then always maintains the H level. [0304] As a result, count circuit 282 counts each time signal PG is activated. Therefore, count circuit 282 counts each time the writing operation is repeated, and each of signals CNT 0 to CNT 3 changes its potential. [0305] Since the other operation is the same as that of FIG. 17 , its description will not be repeated. [0306] By the above operation, the semiconductor memory device in the second embodiment of the present invention decreases the write voltage to be applied to a memory cell each time the writing operation is repeated. As a result, charges can be more accurately accumulated in a memory cell, so that excessive writing can be prevented. Similar effects are produced also with respect to the case of the erasing operation. Third Embodiment In the semiconductor memory device in the second embodiment, in the writing operation, each time the writing operation is repeated, the write voltage is decreased. Alternately, each time the writing operation is repeated, the write voltage can be increased. [0307] FIG. 22 is a circuit diagram showing the configuration of HV detecting circuit 287 of the semiconductor memory device in a third embodiment of the present invention. [0308] Referring to FIG. 22 , HV detecting circuit 287 newly includes transfer gates T 5 to T 8 in place of transfer gates Ti to T 4 different from FIG. 14 . [0309] Transfer gate T 5 and resistive element R 1 are connected in parallel. An output signal of inverter IV 10 is inputted to the gate of an N-channel MOS transistor in transfer gate T 5 . Count signal CNT 3 outputted from count circuit 282 is inputted to inverter IV 10 and the gate of a P-channel MOS transistor. Transfer gate T 6 and resistive element R 2 are connected in parallel. To the gate of an N-channel MOS transistor in transfer gate T 6 , an output signal of inverter IV 11 is inputted. To inverter IV 11 and the gate of the P-channel MOS transistor, count signal CNT 2 outputted from count circuit 282 is inputted. Transfer gate T 7 and resistive element R 3 are connected in parallel. To the gate of an N-channel MOS transistor T 7 , an output signal of inverter IV 12 is inputted. To inverter IV 12 and the gate of a P-channel MOS transistor, count signal CNT 1 outputted from count circuit 282 is inputted. Transfer gate T 8 and resistive element R 4 are connected in parallel. To the gate of an N-channel MOS transistor in transfer gate T 8 , an output signal of inverter IV 13 is inputted. To inverter IV 13 and the gate of a P-channel MOS transistor, count signal CNT 0 outputted from count circuit 282 is inputted. [0310] Since the other configuration is the same as that of FIG. 14 , its description will not be repeated. [0311] FIG. 23 is a timing chart showing the writing operation of a semiconductor memory device in the third embodiment of the present invention. [0312] Referring to FIG. 23 , at time t 1 , semiconductor memory device 100 performs application of the write voltage of the first time. At this time, the other signals PV, ER, and EV outputted from peripheral circuit 281 maintain the H level. At this time, HV detecting circuit 287 , HV oscillator 291 , and HV charge pump 295 operate. As a result, HV charge pump 295 outputs drain voltage IV to be applied to the memory cell. [0313] At this time, all of count signals CNT 0 to CNT 3 outputted from count circuit 282 are at the L level. Since all of transfer gates T 5 to T 8 in HV detecting circuit 287 are turned on, only resistive element R 5 is connected between nodes N 80 and N 81 in HV detecting circuit 287 . The potential of signal HV outputted from HV charge pump 295 is divided by resistive element R 5 and transistor QN 86 . The divided potential is outputted from node N 80 to operational amplifier OP 2 . At this time, operational amplifier OP 2 outputs signal φC 2 of the H level until the voltage of a signal outputted from node N 80 becomes equal to reference potential Vref. As a result, HV charge pump 295 outputs signal HV to the drain of the memory cell. At this time, signal HV is maintained at constant voltage VD 1 . [0314] Similarly, by activation of signal PG, SHGV detecting circuit 285 , SHGV oscillator 289 , and SHGV charge pump 293 operate. As a result, SHGV charge pump 293 outputs gate signal SHGV to be applied to a memory cell. At this time, signal SHGV is maintained at constant voltage VG 1 . [0315] At time t 2 after the write voltage is applied for a predetermined period, signal PG becomes H level- and signal PV becomes L level. As a result, semiconductor memory device 100 starts the verifying operation. Assuming now that when the threshold voltage of a memory cell becomes Vth 1 , sufficient charges are accumulated in storing region 9 R in the memory cell, threshold voltage Vth of the memory cell at time t 2 is lower than Vth 1 . Therefore, comparator 25 determines that charges accumulated in storing region 9 R are insufficient. As a result, signal PG becomes L level at time t 3 , and the write voltage is applied again. [0316] At the time of the verifying operation from time t 2 to t 3 , the count value of count circuit 282 is set to “1”. Therefore, count signal CNT 0 becomes H level. [0317] As a result, transfer gate T 8 in HV detecting circuit 287 is turned off. Therefore, a voltage outputted from node N 80 in HV detecting circuit 287 becomes equal to the potential obtained by dividing the potential of signal IV by resistive elements R 4 and R 5 and transistor QN 86 . Even in the case where the potential of the signal outputted from node N 80 is higher than that at time t 1 , HV detecting circuit 287 outputs signal φC 2 of the L level. [0318] Consequently, voltage VD 2 of signal HV outputted from HV charge pump 295 at time t 2 is higher than voltage VD 1 of signal HV at time t 1 . [0319] For the same reason, voltage VG 2 of signal SHGV outputted from SHGV charge pump 293 becomes higher than voltage VG 1 of signal SHGV at time t 1 . [0320] Subsequently, at time t 4 , a verifying operation is performed. Since the operating method is the same as that of the verifying operation at time t 2 , its description will not be repeated. [0321] By the above operations, until threshold value Vth of the memory cell on which the writing operation is performed becomes Vth 1 , semiconductor memory device 100 repeats application of the write voltage and the verifying operation. Each time the number of application times of the write voltage increases, the voltage to be applied increases. When threshold value Vth of the memory cell exceeds Vth 1 as a result of the verifying operation at time t 5 , comparator 25 outputs pulse signal VERIFY of the H level. Memory control circuit 28 receives signal VERIFY of the H level and finishes the writing operation at time t 6 . [0322] By the above operation, semiconductor memory device 100 in the third embodiment repeats application of the write voltage and the verifying operation at the time of the writing operation. As a result, charges are prevented from being excessively injected into the memory cell. Further, in the third embodiment, by increasing the application voltage each time the number of application times of the write voltage increases, writing operation can be performed at higher speed. Fourth Embodiment [0323] FIG. 24 is a block diagram showing a memory control circuit in a semiconductor memory device in a fourth embodiment of the present invention. [0324] Referring to FIG. 24 , different from FIG. 13 , memory control circuit 28 newly includes a comparator 283 and a storing circuit 284 . [0325] Storing circuit 284 preliminarily stores the maximum number of outputting times of signal PG outputted from peripheral circuit 281 . [0326] Comparator 283 compares count values CNT 0 to CNT 3 outputted from count circuit 282 with the maximum output number of times of signal PG stored in storing circuit 284 . When the count value of count circuit 282 reaches the maximum output number of times of signal PG stored in storing circuit 284 , comparator 283 outputs a signal FIN to peripheral circuit 281 . On receipt of signal FIN, peripheral circuit 281 stops outputting signals PG and PV or signals ER and EV. [0327] Since the other configuration is similar to that of FIG. 13 , its description will not be repeated. [0328] The writing operation of semiconductor memory device 100 including memory control circuit 28 having the above-described circuit configuration will now be described. [0329] FIG. 25 is a flowchart showing the writing operation of the semiconductor memory device in the fourth embodiment. [0330] Referring to FIG. 25 , the operation up to step S 5 is the same as that in FIG. 19 , so that its description will not be repeated. After counting in step S 5 , comparator 283 determines whether the count number of count circuit 282 exceeds the maximum count value stored in storing circuit 284 or not (step S 6 ). In the case where comparator 283 determines that the count value of count circuit 282 does not exceed the maximum count value stored in storing circuit 284 , the program returns again to step S 2 and the write voltage is applied. On the contrary, in the case where comparator 283 determines that the count number of count circuit 282 exceeds the maximum count value stored in storing circuit 284 , memory control circuit 28 determines that an error bit occurs, and finishes the writing operation (step S 7 ). Memory control circuit 28 outputs an error code to the outside of the semiconductor memory device. [0331] By the above operation, the semiconductor memory device in the fourth embodiment can regulate the number of writing operations. With respect to the erasing operation, operations similar to the above are executed. [0332] In the first to fourth embodiments, as an example of the writing operation, the writing operation on storing region 9 R in a memory cell in a state where data is not accumulated in storing regions 9 R and 9 L has been described. However, a writing operation onto storing region 9 R in a state where data is prestored in storing region 9 L can be performed in a manner similar to the case where data is not stored in storing region 9 L. Although the writing operation on a memory cell capable of storing two bits has been described in the first to fourth embodiments, data can be written or erased to/from a memory call capable of storing one bit by a similar operation. Fifth Embodiment [0333] Resistance to the total number of writing operations or the total number of erasing operations in a flash EEPROM having a floating gate and that of an NROM are different from each other. [0334] FIGS. 26A and 26B are graphs showing resistance to the total number of writing operations in a memory cell having a floating gate and that in an MONOS type memory cell, respectively. [0335] As shown in FIG. 26A , in the memory cell having a floating gate, as the total number of writing operations increases, the threshold value decreases. However, as shown in FIG. 26B , in the MONOS type memory cell, as the total number of writing operations increases, the threshold value increases. [0336] Increase in the threshold value causes insufficient erasure at the time of the erasing operation, and there is the possibility that data is destroyed. In the MONOS type memory cell, therefore, it is necessary to suppress increase in the threshold value. In the case of the MONOS type memory cell, to suppress increase in the threshold value, it is sufficient to decrease the write voltage as the total number of writing operations increases. [0337] FIG. 27 is a block diagram showing the configuration of a memory control circuit in a semiconductor memory device in the fifth embodiment of the present invention. [0338] Referring to FIG. 27 , different from FIG. 13 , in place of count circuit 282 , a count circuit 300 is newly disposed and, further, a comparator 301 , a total count circuit 302 , and a pulse generating circuit 303 are added. [0339] Count circuit 300 is a 4-bit counter like count circuit 282 and outputs count signals CNT 0 to CNT 3 . Count circuit 300 is not reset by peripheral circuit 281 . [0340] In response to an internal signal PROGRM which is constantly in an active state when the semiconductor memory device is in a writing operation mode, pulse generating circuit 303 outputs a one-shot pulse signal. [0341] Total count circuit 302 is a 20-bit counter, and counts up each time a one-shot pulse signal is outputted from pulse generating circuit 303 . Therefore, total count circuit 302 counts the total count number of writing operation commands entered after semiconductor memory device 100 is shipped. Total count circuit 302 includes a nonvolatile memory transistor. The nonvolatile memory transistor stores the total number of counts. [0342] Comparator 301 outputs a one-shot pulse signal OSP when the count value of total count circuit 302 becomes a predetermined value. Each time total count circuit 302 reaches, for example, 100, 1000, 10,000, or 100,000, comparator 301 outputs one-shot pulse signal OSP. [0343] Count circuit 300 counts up each time one-shot pulse signal OSP is received. The circuit configuration of SHGV detecting circuit 285 , SHV detecting circuit 286 , HV detecting circuit 287 , and HGV detecting circuit 288 is as shown in FIG. 14 . [0344] As a result, each time count circuit 300 counts up, a sense voltage of each detecting circuit decreases. Thus, as the total number of writing operations increases, the write voltage can be decreased. Sixth Embodiment In the foregoing first to fifth embodiments, the writing operation and the erasing operation in the case of using the MONOS type memory cell shown in FIG. 30 has been described. [0345] However, in the MONOS type memory cell in FIG. 30 , in place of the nitride film 9 playing the role of a charge accumulating layer, a gate insulating film using a granular silicon buried oxide film 90 as a charge accumulating layer as shown in FIG. 28 can be used. Granular silicon buried oxide film 90 includes a plurality of polysilicon grains 91 . The MONOS type memory cell shown in FIG. 28 is expected to realize improved data retaining characteristic and reduced variations in the threshold value at the time of a writing operation as compared with the case of FIG. 30 . [0346] Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.

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