Ramp-up rate control circuit for flash memory charge pump

Abstract

An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current. In one embodiment, the apparatus comprises a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output. The body is adapted for connection to the charge pump output. The apparatus further comprises a control circuit having an input adapted for connection to the charge pump output and an output connected to the bleeder circuit input. The control circuit provides a voltage potential to the input of the current bleeder circuit to control the gate-to-source voltage of the current bleeder circuit transistor. The flow of current through the current path of the current bleeder path is a function of the magnitude of the charge pump output and the gate-to-source voltage of the bleeder circuit transistor. Other embodiments of the apparatus of the present invention are described herein.

Claims

Thus, having described the invention, what is claimed is: 1. An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current, the apparatus comprising: a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output, the body being adapted for connection to the charge pump output; and a control circuit having an input adapted for connection to the charge pump output and an output connected to the bleeder circuit input, the control circuit providing a voltage potential to the input of the current bleeder circuit to control the gate-to-source voltage of the current bleeder circuit transistor; wherein said current bleeder circuit is adapted to permit the flow of current through the current path of the current bleeder circuit as a function of the magnitude of the charge pump output voltage and the gate-to-source voltage of the bleeder circuit transistor. 2. The apparatus according to claim 1 wherein the control circuit comprises: a current controlling circuit having an input defining the control circuit input and an output defining the control circuit output, the connection of the control circuit output and the bleeder circuit input defining a node, the current controlling circuit allowing charge pump bleed current to flow therethrough to the node; and a voltage setting circuit for maintaining the node at the voltage potential to control the gate-to-source voltage of the current bleeder circuit transistor. 3. The circuit according to claim 2 wherein the current controlling circuit comprises: a first circuit having an input defining the current controlling circuit input and an output defining the current controlling circuit output, the first circuit comprising a transistor having a gate, source, and drain, the transistor defining a current path between the source and drain to form a current path between the first circuit input and first circuit output; and a second circuit for outputting a signal to the gate of the first circuit transistor to (1) substantially isolate the first circuit input from the first circuit output when the magnitude of the charge pump output voltage is greater than or equal to a predetermined magnitude, and (2) couple the first circuit input to the first circuit output when the magnitude of the charge pump output voltage is less than the predetermined magnitude. 4. The apparatus according to claim 2 wherein the current controlling circuit comprises: a first circuit having an input defining the current controlling circuit input and an output defining the current controlling circuit output, the first circuit comprising a plurality of transistors, each transistor having a gate, source and drain and defining a current path between the first circuit input and first circuit output; and a second circuit comprising a plurality of networks, each network having an output connected to the gate of a corresponding first circuit transistor, each network determining for each first circuit current path a particular magnitude of the charge pump output voltage wherein the network outputs a signal to the gate of the corresponding first circuit transistor to (1) substantially eliminate current flow through the current path when the magnitude of the charge pump output voltage is greater than or equal to the predetermined magnitude, and (2) allow current flow through the current path when the magnitude of the charge pump output voltage is less than the predetermined magnitude. 5. An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current, the apparatus comprising: a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output, the body being adapted for connection to the charge pump output; and a control circuit comprising: a first circuit having an input adapted for connection to the charge pump output and an output connected to the current bleeder circuit, the first circuit comprising a transistor having a gate, source, and drain, the transistor defining a current path between the source and drain to form a current path between the first circuit input and first circuit output, the connection of the first circuit output and the current bleeder circuit input defining a node, a second circuit for outputting a signal to the gate of the first circuit transistor to (1) substantially isolate the first circuit input from the first circuit output when the magnitude of the charge pump output voltage is greater than or equal to a predetermined magnitude, and (2) couple the first circuit input to the first circuit output when the magnitude of the charge pump output voltage is less than the predetermined magnitude, and a voltage setting circuit for maintaining the node at a voltage potential to control the gate-to-source voltage of the current bleeder circuit transistor; and wherein said current bleeder circuit is adapted to permit the flow of current through the current path of the current bleeder circuit as a function of the magnitude of the charge pump output voltage and the gate-to-source voltage of the bleeder circuit transistor. 6. An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current, the apparatus comprising: a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output, the body being adapted for connection to the charge pump output; and a control circuit comprising: a first circuit having an input adapted for connection to the charge pump output and an output connected to the current bleeder circuit, the first circuit comprising a plurality of transistors, each transistor having a gate, source and drain and defining a current path between the first circuit input and first circuit output, the connection of the first circuit output and the current bleeder circuit input defining a node, and a second circuit comprising a plurality of networks, each network having an output connected to the gate of a corresponding first circuit transistor, each network determining for each first circuit current path a particular magnitude of the charge pump output voltage wherein the network outputs a signal to the gate of the corresponding first circuit transistor to (1) substantially eliminate current flow through the first circuit current path when the magnitude of the charge pump output voltage is greater than or equal to the predetermined magnitude, and (2) allow current flow through the first circuit current path when the magnitude of the charge pump output voltage is less than the predetermined magnitude, and a voltage setting circuit for maintaining the node at a voltage potential to control the gate-to-source voltage of the current bleeder circuit transistor; and wherein the flow of current through the current path of the current bleeder path is a function of the magnitude of the charge pump output and the gate-to-source voltage of the bleeder circuit transistor. 7. An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current, the circuit comprising: a current bleeder circuit having an input, an output adapted for connection to ground potential and a P-FET transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output, the gate being connected to the drain and the body being adapted for connection to the charge pump output; and a control circuit comprising: a current controlling circuit having an input adapted for connection to the charge pump output and an output connected to the input of the current bleeder circuit, the connection of the current controlling circuit output and the bleeder circuit input defining a node, the current controlling circuit allowing charge pump bleed current to flow therethrough to the node, and a voltage-setting circuit for maintaining the node at a voltage potential to control the gate-to-source voltage of the current bleeder circuit transistor; and wherein said current bleeder circuit is adapted to permit the flow of current through the current path of the current bleeder circuit as a function of the magnitude of the charge pump output voltage and the gate-to-source voltage of the bleeder circuit transistor. 8. An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current, the apparatus comprising: a first circuit having an input adapted for connection to the charge pump output and an output adapted for connection to ground potential, the first circuit having a transistor having a gate, source, and drain, the transistor defining a current path between the source and drain to form a current path between the first circuit input and first circuit output; and a second circuit for outputting a signal to the gate of the first circuit transistor to (1) substantially isolate the first circuit input from the first circuit output when the magnitude of the charge pump output voltage is greater than or equal to a predetermined magnitude, and (2) couple the first circuit input to the first circuit output when the magnitude of the charge pump output voltage is less than the predetermined magnitude. 9. An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current, the apparatus comprising: a first circuit having an input adapted for connection to the charge pump output and an output adapted for connection to ground potential, the first circuit having a plurality of transistors, each transistor having a gate, source and drain and defining a current path between the first circuit input and first circuit output; and a second circuit comprising a plurality of networks, each network having an output connected to the gate of a corresponding first circuit transistor, each network determining for each current path a particular magnitude of the charge pump output voltage wherein the network outputs a signal to the gate of the corresponding transistor to (1) substantially eliminate current flow through the first circuit current path when the magnitude of the charge pump output voltage is greater than or equal to the predetermined magnitude, and (2) allow current flow through the first circuit current path when the magnitude of the charge pump output voltage is less than the predetermined magnitude.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to charge pumps, and more particularly, to a circuit for controlling the charge pump ramp-up rate. 2. Problem to be Solved Flash memory devices are typically nonvolatile memories that are reprogrammable. Such devices are Electrically Erasable Programmable Read Only Memories (EEPROM). Typically, the flash memory cells are arranged in an array and are located at the intersections of rows (word lines) and columns (bit lines). A cell is typically comprised of a floating gate transistor and a select transistor. The floating gate transistors are programmed by grounding the control electrode and raising the drain voltage. Tunneling causes electrons to be transferred from the substrate to the floating-gate through a thin tunneling oxide layer. A programming voltage pulse between about 18-20 volts may be needed to induce tunneling. As charge builds up on the floating gate, the electric field is reduced, decreasing electron flow. During programming, the select transistor is used to isolate the unselected memory cells that are located on the same column. Erasing of the memory cell is accomplished by applying a high programming voltage pulse to the control electrode of the floating-gate transistor. High programming voltages result in overstress of the flash memory device. Such overstress limits the number of programming cycles performed on a flash memory device thereby shortening the useful lifetime of the memory device. The peak tunneling current has a direct bearing on the reliability and service life of the memory device. The peak tunneling current is directly related to the ramp-up rate of the programming voltage pulse outputted by a charge pump. If the ramp-up rate of the programming voltage pulse is too high, the peak tunneling current may overstress the thin tunneling oxide layer resulting in reduced reliability and shortened service life. One attempt at solving the aforementioned problem is the utilization of a weak charge pump configuration. Such a configuration uses several pumps, each of which using smaller pump-capacitor values and lower pump-oscillator frequencies. However, for flash memory applications, the connection scheme of the charge pumps is complex, requires a relatively large chip area and consumes a relatively large amount of power. Furthermore, weak charge pumps provide a ramp-up rate that is too low thereby increasing the time required for programming and erasing operations. Thus, it is an object of the present invention to provide a control circuit for accurately and efficiently controlling the ramp-up rate of a charge pump used for programming flash memory devices. It is another object of the present invention to provide a control circuit for controlling the ramp-up rate of a charge pump used for programming and erasing a flash memory device so as to prevent overstressing the flash memory device. It is a further object of the present invention to provide a control circuit for controlling the ramp-up rate of a charge pump that allows for the use of only one charge pump for performing operations on flash memory devices. It is another object of the present invention to provide a control circuit for controlling the ramp-up rate of a charge pump which can be implemented with modern sub-half micron CMOS technology. SUMMARY OF THE INVENTION The above and other objects and advantages, which will be apparent to those skilled in the art, are achieved in the present invention which is directed to, in a first aspect, an apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current, the apparatus comprising: a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output, the body being adapted for connection to the charge pump output; and a control circuit having an input adapted for connection to the charge pump output and an output connected to the bleeder circuit input, the control circuit providing a voltage potential to the input of the current bleeder circuit to control the gate-to-source voltage of the current bleeder circuit transistor; and wherein the flow of current through the current path of the current bleeder path is a function of the magnitude of the charge pump output and the gate-to-source voltage of the bleeder circuit transistor. In a related aspect, the present invention is directed to an apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current, the apparatus comprising: a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output, the body being adapted for connection to the charge pump output; and a control circuit comprising: a first circuit having an input adapted for connection to the charge pump output and an output connected to the current bleeder circuit input, the first circuit comprising a transistor having a gate, source, and drain and defining a current path between the source and drain to form a current path between the first circuit input and first circuit output, the connection of the first circuit output and the bleeder circuit input defining a node, a second circuit for outputting a signal to the gate of the first circuit transistor to (1) substantially isolate the first circuit input from the first circuit output when the magnitude of the charge pump output voltage is greater than or equal to a predetermined magnitude, and (2) couple the first circuit input to the first circuit output when the magnitude of the charge pump output voltage is less than the predetermined magnitude, and a voltage setting circuit for maintaining the node at a voltage potential to control the gate-to-source voltage of the current bleeder circuit transistor; wherein the flow of current through the current path of the current bleeder circuit is a function of the magnitude of the charge pump output and the gate-to-source voltage of the bleeder circuit transistor. In a further aspect, the present invention is directed to an apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current, the apparatus comprising: a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output, the body being adapted for connection to the charge pump output; and a control circuit comprising: a first circuit having an input adapted for connection to the charge pump output and an output connected to the current bleeder circuit input, the first circuit comprising a plurality of transistors, each having a gate, source and drain and defining a current path between the first circuit input and first circuit output, the connection of the first circuit output and the bleeder circuit input defining a node, and a second circuit comprising a plurality of networks, each network having an output connected to the gate of a corresponding first circuit transistor, each network determining for each first circuit current path a particular magnitude of the charge pump output voltage wherein the network outputs a signal to the gate of the corresponding first circuit transistor to (1) substantially eliminate current flow through the first circuit current path when the magnitude of the charge pump output voltage is greater than or equal to the predetermined magnitude, and (2) allow current flow through the first circuit current path when the magnitude of the charge pump output voltage is less than the predetermined magnitude, and a voltage setting circuit for maintaining the node at a voltage potential to control the gate-to-source voltage of the current bleeder circuit transistor; wherein the flow of current through the current path of the current bleeder path is a function of the magnitude of the charge pump output and the gate-to-source voltage of the bleeder circuit transistor. In another aspect, the present invention is directed to an apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current, the apparatus comprising: a first circuit having an input adapted for connection to the charge pump output and an output adapted for connection to ground potential, the first circuit having a transistor having a gate, source, and drain, the transistor defining a current path between the source and drain to form a current path between the first circuit input and first circuit output; and a second circuit for outputting a signal to the gate of the first circuit transistor to (1) substantially isolate the first circuit input from the first circuit output when the magnitude of the charge pump output voltage is greater than or equal to a predetermined magnitude, and (2) couple the first circuit input to the first circuit output when the magnitude of the charge pump output voltage is less than the predetermined magnitude. In a further aspect, the present invention is directed to an apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current, the apparatus comprising: a first circuit having an input adapted for connection to the charge pump output and an output adapted for connection to ground potential, the first circuit having a plurality of transistors, each having a gate, source and drain and defining a current path between the first circuit input and first circuit output; and a second circuit comprising a plurality of networks, each network having an output connected to the gate of a corresponding first circuit transistor, each network determining for each current path a particular magnitude of the charge pump output voltage wherein the network outputs a signal to the gate of the corresponding transistor to (1) substantially eliminate current flow through the first circuit current path when the magnitude of the charge pump output voltage is greater than or equal to the predetermined magnitude, and (2) allow current flow through the first circuit current path when the magnitude of the charge pump output voltage is less than the predetermined magnitude. BRIEF DESCRIPTION OF THE DRAWINGS The features of the invention are believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The figures are for illustration purposes only and are not drawn to scale. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which: FIG. 1A is a block diagram of the charge pump ramp-up rate control apparatus of the present invention. FIG. 1B is a circuit diagram of one embodiment of the charge pump ramp-up rate control circuit of the present invention. FIG. 1C is a block diagram of one embodiment of a control circuit shown in FIG. 1B. FIG. 2A is a circuit diagram of another embodiment of the present invention. FIG. 2B is a graph of the operating characteristics of the embodiment of FIG. 2A. FIG. 3A is a circuit diagram of a further embodiment of the present invention. FIG. 3B is a graph of the operating characteristics of the embodiment shown in FIG. 3A. FIG. 4 is a block diagram of a preferred embodiment of the present invention. FIG. 5 is a circuit diagram of the preferred embodiment shown in FIG. 4. FIG. 6 is a graph showing charge pump ramp-up rate without the ramp-up rate control apparatus of the present invention, with the ramp-up rate control apparatus of the present invention configured as shown in FIG. 2A and with the ramp-up rate control apparatus of the present invention configured as shown in FIG. 5. DESCRIPTION OF THE PREFERRED EMBODIMENTS In describing the preferred embodiment of the present invention, reference will be made herein to FIGS. 1-6 of the drawings in which like numerals refer to like features of the invention. Features of the invention are not necessarily shown to scale in the drawings. Referring to FIG. 1A, ramp-up rate control circuit 10 of the present invention generally consists of a self-controlled bleeding circuit for controlling the ramp-up speed of charge pump 12. The circuit includes input 14 connected to the charge pump output and output 16 connected to ground potential. The circuit includes control input 18 connected to the charge pump output. The circuit also includes a current path connected between input 14 and output 16. Circuit 10 is configured such that the conductivity of the current path is controlled by the magnitude of the charge pump voltage such that when the charge pump output voltage inputted to control input 18 is less than a predetermined magnitude, the current path is conductive and provides a current bleed path between the charge pump output and ground potential. When the magnitude of the charge pump output voltage inputted to circuit 10 is greater than or equal to the predetermined magnitude, the current flow path becomes non-conductive or highly resistive thereby substantially electrically isolating input 14 from output 16 to prevent charge pump bleed current from flowing to ground potential. Thus, control circuit 10 regulates the flow of charge pump bleed current Ip to ground potential by providing a current bleed path to ground potential upon the occurrence of predetermined conditions that are determined by the magnitude of the charge pump output voltage V out . Capacitor 13, shown in phantom, represents a capacitive load presented by a flash memory device to the output of charge pump 12. The charge pump current can be any magnitude, depending on the size of the charge pump. Typically, the charge pump current is between about 0.5 milliampere and 0.5 ampere. Ramp-up rate control circuit 10 may take the form of any one of the configurations discussed below. Other configurations embodying the concept of the present invention will be apparent to one skilled in the art. One embodiment of circuit 10 is shown in FIG. 1B and comprises p-channel MOSFET ("FET") 20 and control circuit 11. FET 20 functions as a current bleeder circuit. Circuit 11 has an input coupled to input 14 and an output coupled to source 24 of FET 20. The connection of the output of circuit 11 and source 24 defines node 13. Circuit 11 functions to provide a substantially constant voltage potential at node 13. In addition, circuit 11 is preferably configured to either pass through essentially all of the charge pump bleed current I P or act as an additional current flow control. Since gate 21 of FET 20 is connected to drain 26 which is connected to ground potential via output 16, the gate voltage V G is at ground potential. Thus, |V GS | of FET 20 is approximately equal to the voltage at node 13. The body or n-well 22 of FET 20 is connected to control input 18 which is connected to output voltage V out of charge pump 12. Thus, the body potential of FET 20 is modulated by the charge pump output voltage V out such that as V out increases, the threshold voltage |V TH | of FET 20 also increases. When |V GS | of FET 20 is greater than the threshold voltage |V TH |, an electrically conductive path is produced between source 24 and drain 26 thereby allowing current I B to flow from source 24 to drain 26. As the threshold voltage |V TH | increases and becomes greater than |V GS |, the resistance of the channel from source 24 to drain 26 increases which effects a decrease in the flow of current I B from source 24 to drain 26. Since control circuit 11 determines the magnitude of |V GS | of FET 20, circuit 11 in effect determines the magnitude of charge pump output voltage at which the current path from source 24 to drain 26 becomes highly resistive. Thus, FET 20 functions as a substrate-controlled switch that regulates the flow of bleeder current I B to ground potential as a function of the magnitude of the charge pump output voltage applied to the body 22 of FET 20 and the |V GS | of FET 20 as determined by circuit 11. Circuit 11 can be realized by a variety of circuits. A block diagram of circuit 11 is shown in FIG. 1C. Circuit 11 is comprised of voltage setting circuit 106 which effects a substantially constant voltage at node 13' while minimizing the current flow I" so that I' is substantially the same as I"'. One embodiment of circuit 106 is shown in FIG. 5. Circuit 11 further comprises current-controlling circuit 102' that may either pass through essentially all of the current I P to I' or may act as an additional current flow control. Embodiments of circuit 102' that function as additional current flow controls include circuits 102A and 102B of FIGS. 2A and 3A, respectively. Another embodiment of the ramp-up rate control circuit of the present invention is shown as circuit 102A in FIG. 2A. Circuit 102A comprises diodes 28 arranged in series, inverter 30, and n-channel MOSFET 34. Drain 38 of FET 34 is connected to input 14 which is connected to the charge pump output. Source 40 of FET 34 is connected to output 16 which is connected to ground potential. Inverter 20 is preferably in the form of an integrated circuit. Diodes 28 are arranged in series so as to act as voltage shifting elements that provide a series of voltage drops. The anode of first diode 28a is connected to control input 18 which is connected to the charge pump output voltage V out . The cathode of the last diode 28b is connected to input 32 of inverter 30. The number of diodes connected in series determines voltage V 1 at input 32 of inverter 30. Thus, diodes 28 convert the charge pump output voltage V out to voltage V 1 which is less than V out . The magnitude of voltage V 1 is either in a first range of magnitudes that constitute a logic "1" (or high input) or a second range of magnitudes that constitute a logic "0" (or low input) to the inverter. A single zener diode may be used in place of diodes 28. When the magnitude of V 1 is a logic "0", inverter 30 outputs a voltage V 2 that is a logic "1". Voltage V 2 is inputted into gate 36 of FET 34. When a logic "1" voltage is inputted into gate 36, an electrically conductive path is established between drain 38 and source 40 thereby allowing charge pump bleed current I p to flow to ground potential. When V 1 is a logic "1", inverter 30 outputs voltage V 2 that is a logic "0". When a logic "0" voltage is inputted into gate 36, drain 38 becomes substantially electrically isolated from source 40 thereby substantially eliminating the flow of charge pump bleed current I p to ground potential. A p-channel MOSFET, with the appropriate circuit modifications, may be used in place of n-channel MOSFET 34. The number of diodes 28 determines the magnitude of the charge pump output voltage V out that causes FET 34 to substantially electrically isolate drain 38 from source 40 so as to "turn off" the current bleeding path between the charge pump output and ground potential. Thus, diodes 28 and inverter 30 form a network that controls the potential of gate 36 so as to control the flow of current from drain 38 to source 40. The charge pump output voltage V out having a magnitude that turns off the current bleeding path is referred to herein as V OFF . As shown by the graph of FIG. 2B, nine (9) diodes effects substantial elimination of the current path to ground potential when the charge pump output voltage V out is about 7.32 volts. Similarly, when ten (10) and eleven (11) diodes are used, the current bleeding path is turned off when V out is about 7.81 volts and about 8.41 volts, respectively. The width of the n-channel of FET 34 determines the maximum current flowing through the current bleed path. FIG. 3A shows an alternate embodiment of the ramp-up control circuit of the present invention. Circuit 102B comprises multiple-current bleed paths wherein each path is configured as the circuitry shown in FIG. 2A. As shown in FIG. 3A, four (4) current bleed paths are used. Multiple-bleeding paths effect accurate control of bleeding current to ground potential for varying magnitudes of charge pump output voltage V out . The total charge pump bleed current I P is comprised of the four branch currents I 1 , I 2 , I 3 and I 4 . Each current bleed path has a corresponding turn-off voltage (V OFF ) that will turn off that particular bleed path. The first current bleed path is through n-channel FET 42 which is controlled by inverter 44 and diodes 46. The second current bleed path is through n-channel FET 48 which is controlled by inverter 50 and diodes 46 and 52. The third current bleed path is through FET 54 which is controlled by inverter 56 and diodes 46, 52 and 58. Similarly, the fourth current bleed path is through FET 60 which is controlled by inverter 62 and diodes 46, 52, 58 and 64. Although four (4) current paths are shown, the embodiment shown in FIG. 3A may be modified to have more or less than four (4) current paths. It is to be understood that the quantities of diodes 46, 52, 58 and 64 shown in FIG. 3A are for purposes of discussion only. The actual required quantities of diodes depends upon the desired operating characteristics. Referring to FIGS. 3A, 3B and Table 1, the first current bleed path is turned off first when charge pump output voltage V out is about 5.78 volts. When V out is about 5.78 volts, diodes 46 produce a series of voltage drops that produce a voltage V 01 which has a magnitude that constitutes a logic "1" voltage. In response to this logic "1" voltage, inverter 44 outputs a logic "0" voltage level which turns-off FET 42 thereby substantially eliminating the flow of current I 1 through FET 42. Increasing the number of diodes 46 will result in a higher charge pump output voltage being needed to turn off the first current bleed path. Similarly, fewer diodes will result in a lower charge pump output voltage being needed to turn off the first current bleed path. The second current bleed path is turned off when charge pump output voltage V out is about 7.6 volts. When V out is about 7.6 volts, diodes 46 and 52 produce a series of voltage drops that produce a voltage V 02 that has a magnitude that constitutes a logic "1" voltage. In response to this logic "1" voltage, inverter 50 outputs a logic "0" voltage level which turns-off FET 48 so as to substantially eliminate the flow of current I 2 through FET 48. The third current bleed path is turned off when charge pump output voltage V out is about 9.5 volts. When V out is about 9.5 volts, diodes 46, 52 and 58 produce a series of voltage drops that produce a voltage V 03 that has a magnitude that constitutes a logic "1" voltage. In response to this logic "1" voltage, inverter 56 outputs a logic "0" voltage level which turns-off FET 54 so as to substantially eliminate the flow of current I 3 through FET 54. The fourth current bleed path is turned off when charge pump output voltage V out about 11.43 volts. When V out is about 11.43 volts, diodes 46, 52, 58 and 64 produce a series of voltage drops that produce a voltage V 04 that has a magnitude that constitutes a logic "1" voltage. In response to this logic "1" voltage, inverter 62 outputs a logic "0" voltage level which turns-off FET 60 so as to substantially eliminate the flow of current I 4 through FET 60. Table 1 shows the bleed path current contributed to current I P for varying magnitudes of charge pump output voltage V out . ______________________________________Total Bleeding Leakage(I.sub.P) Output Voltage Range______________________________________I.sub.P = I.sub.1 + I.sub.2 + I.sub.3 + I.sub.4 2.5 < V.sub.out < 5.78I.sub.P = I.sub.2 + I.sub.3 + I.sub.4 5.78 < V.sub.out < 7.60I.sub.P = I.sub.3 + I.sub.4 7.60 < V.sub.out < 9.50I.sub.P = I.sub.4 9.5 < V.sub.out < 11.43I.sub.P = 0 11.43 < V.sub.out______________________________________ FIG. 4 shows a block diagram of a preferred embodiment of the present invention. FIG. 5 is a circuit diagram of the preferred embodiment of FIG. 4. Ramp-up control circuit 100 comprises current bleeder circuit 102, voltage-setting circuit 106 and current bleeder circuit 104. These circuits cooperate to completely turn off the current bleed path to prevent the flow of charge pump bleed current to ground potential when the magnitude of V out is at a predetermined level. As described above, circuit 102 acts as a switch through which the flow of charge pump bleed current I p is controlled. The control of the flow of current is a function of the magnitude of the charge pump voltage V out . Preferably, circuit 102 is configured as circuit 102B shown in FIG. 3A. The sources of FETs used in circuit 102B are connected together to form a single current output line 110 which is inputted into current bleeder circuit 104. Circuit 102 includes series diodes associated with each current bleed path, as described above for FIG. 3A, for determining a corresponding magnitude of V out (V OFF ) that will turn off that particular bleed path. The series diodes associated with each current path produce a voltage having a magnitude that constitutes a logic "0" magnitude when the charge pump output voltage magnitude is less than V OFF . The series diodes also produce a voltage having a magnitude that constitutes a logic "1" magnitude when the charge pump output voltage magnitude is greater than or equal to V OFF . As described above, an inverter associated with the current bleed path receives that voltage produced by the series diodes and in response to such voltage, controls a corresponding FET to permit or inhibit charge pump bleed current I p to flow from the FET drain to the FET source. Preferably, circuit 104 is configured as the p-channel FET shown in FIG. 1B. Circuit 104 comprises FET 112 which has its source 114 connected to node 110. Node 110 is connected to the sources of all the FETs in current bleeder circuit 102. The body or n-well 116 of FET 112 is connected to the charge pump output voltage V out . Thus, the body potential of FET 112 is modulated by the charge pump output voltage. Drain 118 is connected to gate 120 and to ground potential via output 16. Circuit 104 functions in the same manner as described above for the circuit shown in FIG. 1B. Voltage-setting circuit 106 fixes the node at 110 and therefore controls V GS of FET 112 of circuit 104. When the |V GS | is less than the threshold voltage |V TH |, FET 112 is turned off, i.e. current will not flow from source 114 to drain 118. Voltage-setting circuit 106 comprises differential amplifier 126 and constant current source 128. Differential amplifier 126 comprises FETs 130, 132, 134 and 136. Constant current source 128 comprises FETs 144, 146 and 148 which are configured in a manner well known in the art. A reference voltage V REF is applied to the gate of FET 130. Thus, when circuit 104 is operating such that current I B is flowing to ground potential, the voltage at node 110 is the same as V REF . Preferably, V REF is about 4.0 volts and the supply voltage V DD is about 5.0 volts. Due to the high input resistance of FET 136, current I A flowing into the gate of FET 136 is very small, i.e. in the picoampere range. Node 140 is defined by the anode of diode 142, the drain of FET 136 and the source of FET 134. Diode 142 acts as a blocking diode and directs the flow of current I C from node 140 to node 110 and prevents current from flowing into voltage-setting circuit 106. Current I C is minimal (in the picoampere range) and thus, substantially the entire current flow I B is comprised of the portion of charge pump bleed current I P flowing through the current bleed paths produced by circuit 102. When the charge pump output voltage V out reaches a predetermined magnitude, the threshold voltage |V TH | of FET 112 becomes greater than |V GS | thus "turning off" FET 112 and preventing current flow from flowing therethrough. Thus, voltage-setting circuit 106 controls the V GS of both the p-channel FETs of circuit 104 and the source voltage of the n-channel FETs of circuit 102 which effects control of the amount of charge pump current flowing through the bleeding path to ground potential. The charge pump ramp-up rate or speed is controlled by varying the amount of current flowing through the bleed path. As the charge pump output voltage V out is gradually increased, the resistance through the current bleeding path increases. When the charge pump output voltage V out reaches a predetermined level, the bleeding path will be completely turned off by both circuits 102 and 104. FIG. 6 shows a comparison of the charge pump ramp-up rate with and without the ramp-up rate control circuit of the present invention. Referring to Curve A, the ramp-up time without the ramp-up rate control circuit of the present-invention is about 3 us (microseconds) for a maximum charge pump output voltage V out of about 12.96 volts. Referring to Curve B, the ramp-up time with the circuit 102B of FIG. 3A is about 8 us (microseconds) for the same maximum charge pump output voltage. Referring to Curve C, the ramp-up time with the circuit 100 of FIG. 5 is about 12 us (microseconds) for the same maximum charge pump output voltage. Thus, the ramp-up rate of the programming voltage pulse is significantly reduced thereby preventing the peak tunneling current from overstressing the thin tunneling oxide layer of the flash memory device. The slope of Curves B and C shown in FIG. 6 may be varied by adjusting the operating parameters of the circuits 102, 104 and voltage-setting circuit 106. For example, the channel widths of the FETs in circuits 102 and 104 may be varied to increase or decrease the current flowing through the FETs. While the present invention has been particularly described, in conjunction with a specific preferred embodiment, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.

Description

Topics

Download Full PDF Version (Non-Commercial Use)

Patent Citations (46)

    Publication numberPublication dateAssigneeTitle
    US-2873387-AFebruary 10, 1959Rca CorpControllable transistor clipping circuit
    US-3321642-AMay 23, 1967Northern Electric CoFloating back diode limiter
    US-3369129-AFebruary 13, 1968IbmCurrent limiter employing field effect devices
    US-3403265-ASeptember 24, 1968Westinghouse Electric CorpTemperature compensated tunnel diode voltage comparator circuit
    US-3535549-AOctober 20, 1970Singer CoFunction generator
    US-3603811-ASeptember 07, 1971American Optical CorpTwo-terminal bipolar self-powered low current limiter
    US-3878403-AApril 15, 1975Bell Telephone Labor IncLimit circuits
    US-3946251-AMarch 23, 1976Hitachi, Ltd.Pulse level correcting circuit
    US-4326134-AApril 20, 1982Xicor, Inc.Integrated rise-time regulated voltage generator systems
    US-4488060-ADecember 11, 1984Xicor, Inc.High voltage ramp rate control systems
    US-4739282-AApril 19, 1988Anadigics, Inc.Current bleeder amplifier with positive feedback
    US-4958093-ASeptember 18, 1990International Business Machines CorporationVoltage clamping circuits with high current capability
    US-5041889-AAugust 20, 1991Siemens AktiengesellschaftMonolithically integratable transistor circuit for limiting transient positive high voltages, such as ESD pulses caused by electrostatic discharges on electric conductors
    US-5075572-ADecember 24, 1991Texas Instruments IncorporatedDetector and integrated circuit device including charge pump circuits for high load conditions
    US-5120668-AJune 09, 1992Ibm CorporationMethod of forming an inverse T-gate FET transistor
    US-5157289-AOctober 20, 1992Grumman Aerospace CorporationFET adaptive limiter with high current FET detector
    US-5172409-ADecember 15, 1992Motorola, Inc.Precision FET control loop
    US-5182468-AJanuary 26, 1993Ibm CorporationCurrent limiting clamp circuit
    US-5233314-AAugust 03, 1993Cyrix CorporationIntegrated charge-pump phase-locked loop circuit
    US-5234535-AAugust 10, 1993International Business Machines CorporationMethod of producing a thin silicon-on-insulator layer
    US-5247241-ASeptember 21, 1993Silicon Systems, Inc.Frequency and capacitor based constant current source
    US-5258318-ANovember 02, 1993International Business Machines CorporationMethod of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon
    US-5276338-AJanuary 04, 1994International Business Machines CorporationBonded wafer structure having a buried insulation layer
    US-5359299-AOctober 25, 1994Gennum CorporationHigh speed and low drift charge pump circuit
    US-5365121-ANovember 15, 1994Motorola Inc.Charge pump with controlled ramp rate
    US-5391510-AFebruary 21, 1995International Business Machines CorporationFormation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
    US-5405795-AApril 11, 1995International Business Machines CorporationMethod of forming a SOI transistor having a self-aligned body contact
    US-5459437-AOctober 17, 1995Integrated Device TechnologyLogic gate with controllable hysteresis and high frequency voltage controlled oscillator
    US-5466625-ANovember 14, 1995International Business Machines CorporationMethod of making a high-density DRAM structure on SOI
    US-5484738-AJanuary 16, 1996International Business Machines CorporationMethod of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits
    US-5521399-AMay 28, 1996International Business Machines CorporationAdvanced silicon on oxide semiconductor device structure for BiCMOS integrated circuit
    US-5528062-AJune 18, 1996International Business Machines CorporationHigh-density DRAM structure on soi
    US-5561385-AOctober 01, 1996Lg Semicon Co., Ltd.Internal voltage generator for semiconductor device
    US-5567533-AOctober 22, 1996W. R. Grace & Co.-Conn.Antifog film laminates
    US-5573964-ANovember 12, 1996International Business Machines CorporationMethod of making thin film transistor with a self-aligned bottom gate using diffusion from a dopant source layer
    US-5599725-AFebruary 04, 1997International Business Machines CorporationMethod for fabricating a MOS transistor with two-layer inverse-T tungsten gate structure
    US-5622881-AApril 22, 1997International Business Machines CorporationPacking density for flash memories
    US-5633522-AMay 27, 1997International Business Machines CorporationCMOS transistor with two-layer inverse-T tungsten gate
    US-5643813-AJuly 01, 1997International Business Machines CorporationPacking density for flash memories by using a pad oxide
    US-5663578-ASeptember 02, 1997International Business Machines CorporationThin film transistor with self-aligned bottom gate
    US-5675164-AOctober 07, 1997International Business Machines CorporationHigh performance multi-mesa field effect transistor
    US-5689127-ANovember 18, 1997International Business Machines CorporationVertical double-gate field effect transistor
    US-5729039-AMarch 17, 1998International Business Machines CorporationSOI transistor having a self-aligned body contact
    US-5736891-AApril 07, 1998International Business Machines CorporationDischarge circuit in a semiconductor memory
    US-5753525-AMay 19, 1998International Business Machines CorporationMethod of making EEPROM cell with improved coupling ratio
    US-5759907-AJune 02, 1998International Business Machines CorporationMethod of making large value capacitor for SOI

NO-Patent Citations (1)

    Title
    A Quick Boosting Charge Pump Circuit for High Density and Low Voltage Flash Memories , Tanzawa et al., 1994.

Cited By (18)

    Publication numberPublication dateAssigneeTitle
    US-2006109729-A1May 25, 2006Sharp Kabushiki KaishaSemiconductor storage device and mobile electronic device
    US-2007124574-A1May 31, 2007Standard Microsystems CorporationRamp rate closed-loop control (RRCC) for PC cooling fans
    US-2008298131-A1December 04, 2008Choy Jon S, Chrudimsky David WIntegrated circuit featuring a non-volatile memory with charge/discharge ramp rate control and method therefor
    US-2009097312-A1April 16, 2009Evrim BinbogaControlled ramp rates for metal bitlines during write operations from high voltage driver for memory applications
    US-2010215510-A1August 26, 2010Chao-Ming Tsai, Kern Lynn RRPM Controller Using Drive Profiles
    US-6052022-AApril 18, 2000Samsung Electronics Co., Ltd.Voltage boosting circuits having over-voltage protection circuits therein
    US-6052305-AApril 18, 2000Hyundai Electronics Industries Co., Ltd.Erasing circuit for a flash memory device having a triple well structure
    US-6245613-B1June 12, 2001International Business Machines CorporationField effect transistor having a floating gate
    US-6400605-B1June 04, 2002Summit Microelectronics, Inc.Method and system for pulse shaping in test and program modes
    US-6980047-B1December 27, 2005Taiwan Semiconductor Manufacturing CompanyLow power high voltage ramp-up control circuit
    US-7203118-B2April 10, 2007Sharp Kabushiki KaishaSemiconductor storage device and mobile electronic device
    US-7425812-B2September 16, 2008Standard Microsystems CorporationRamp rate closed-loop control (RRCC) for PC cooling fans
    US-7542351-B2June 02, 2009Freescale Semiconductor, Inc.Integrated circuit featuring a non-volatile memory with charge/discharge ramp rate control and method therefor
    US-7630250-B2December 08, 2009Spansion LlcControlled ramp rates for metal bitlines during write operations from high voltage driver for memory applications
    US-7863849-B2January 04, 2011Standard Microsystems CorporationDelta-sigma modulator for a fan driver
    US-8241008-B2August 14, 2012Standard Microsystems CorporationRPM controller using drive profiles
    US-9212664-B2December 15, 2015Standard Microsystems CorporationRPM controller using drive profiles
    WO-2009052181-A1April 23, 2009Spansion LlcControlled ramp rates for metal bitlines during write operations from high voltage driver for memory applications